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2019-02-12drivers: soc: xilinx: Add ZynqMP power domain driverJolly Shah3-0/+331
The zynqmp-genpd driver communicates the usage requirements for logical power domains / devices to the platform FW. FW is responsible for choosing appropriate power states, taking Linux' usage information into account. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-12drivers: soc: xilinx: Add ZynqMP PM driverRajan Vaja3-0/+190
Add ZynqMP PM driver. PM driver provides power management support for ZynqMP. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-16soc: xilinx: Fix Kconfig alignmentMichal Simek1-10/+10
Tabs should be used for alignment instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-16soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdivGustavo A. R. Silva1-1/+1
Currently clkoutdiv is being operated on by a logical && operator rather than a bitwise & operator. This looks incorrect as these should be bit flag operations. Addresses-Coverity-ID: 1463959 ("Logical vs. bitwise operator") Fixes: cee8113a295a ("soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver") Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Acked-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-16soc: xilinx: xlnx_vcu: Depends on HAS_IOMEM for xlnx_vcuDhaval Shah1-0/+1
xlnx_vcu driver uses devm_ioremap_nocache, which is included only when HAS_IOMEM is enabled. drivers/soc/xilinx/xlnx_vcu.o: In function `xvcu_probe': xlnx_vcu.c:(.text+0x116): undefined reference to `devm_ioremap_nocache' xlnx_vcu.c:(.text+0x1ae): undefined reference to `devm_ioremap_nocache' Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-08soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driverDhaval Shah3-0/+646
Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-08soc: xilinx: Create folder structure for soc specific driversMichal Simek2-0/+5
Create directory structure with Makefile/Kconfig for adding xilinx soc specific drivers. Signed-off-by: Michal Simek <michal.simek@xilinx.com>