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2020-09-25soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe apiDennis YC Hsieh1-2/+3
Add clear parameter to let client decide if event should be clear to 0 after GCE receive it. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://lore.kernel.org/r/1594136714-11650-9-git-send-email-dennis-yc.hsieh@mediatek.com [mb: fix commit message] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25soc: mediatek: cmdq: add jump functionDennis YC Hsieh1-0/+13
Add jump function so that client can jump to any address which contains instruction. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Link: https://lore.kernel.org/r/1594136714-11650-8-git-send-email-dennis-yc.hsieh@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25soc: mediatek: cmdq: add write_s_mask value functionDennis YC Hsieh1-0/+21
add write_s_mask_value function in cmdq helper functions which writes a constant value to address with mask and large dma access support. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Link: https://lore.kernel.org/r/1594136714-11650-7-git-send-email-dennis-yc.hsieh@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25soc: mediatek: cmdq: add write_s value functionDennis YC Hsieh1-0/+14
add write_s function in cmdq helper functions which writes a constant value to address with large dma access support. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Link: https://lore.kernel.org/r/1594136714-11650-6-git-send-email-dennis-yc.hsieh@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25soc: mediatek: cmdq: add read_s functionDennis YC Hsieh1-0/+15
Add read_s function in cmdq helper functions which support read value from register or dma physical address into gce internal register. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Link: https://lore.kernel.org/r/1594136714-11650-5-git-send-email-dennis-yc.hsieh@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25soc: mediatek: cmdq: add write_s_mask functionDennis YC Hsieh1-0/+23
add write_s_mask function in cmdq helper functions which writes value contains in internal register to address with mask and large dma access support. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Link: https://lore.kernel.org/r/1594136714-11650-4-git-send-email-dennis-yc.hsieh@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25soc: mediatek: cmdq: add write_s functionDennis YC Hsieh1-0/+19
add write_s function in cmdq helper functions which writes value contains in internal register to address with large dma access support. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Link: https://lore.kernel.org/r/1594136714-11650-3-git-send-email-dennis-yc.hsieh@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25soc: mediatek: cmdq: add address shift in jumpDennis YC Hsieh1-1/+2
Add address shift when compose jump instruction to compatible with 35bit format. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Link: https://lore.kernel.org/r/1594136714-11650-2-git-send-email-dennis-yc.hsieh@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25soc: mediatek: mtk-infracfg: Fix kerneldocKrzysztof Kozlowski1-2/+2
Fix W=1 compile warnings (invalid kerneldoc): drivers/soc/mediatek/mtk-infracfg.c:34: warning: Function parameter or member 'infracfg' not described in 'mtk_infracfg_set_bus_protection' drivers/soc/mediatek/mtk-infracfg.c:34: warning: Excess function parameter 'regmap' description in 'mtk_infracfg_set_bus_protection' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200729074415.28393-1-krzk@kernel.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25soc: aspeed-lpc-ctrl: Fix driver nameJoel Stanley1-1/+1
Clarify the string now that it supports the AST2600 too. Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-09-25soc: aspeed-lpc-ctrl: Fix whitespaceJoel Stanley1-2/+2
Some misaligned indentation I noticed when applying another patch. Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-09-25soc: aspeed-lpc-ctrl: LPC to AHB mapping on ast2600Joel Stanley1-0/+17
The ast2600 disables the mapping of AHB memory regions by default, only allowing the LPC window to point to SPI NOR. In order to point the window to any AHB address, an ast2600 specific bit must be toggled. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20200312121413.294384-1-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-09-25soc: aspeed-lpc-ctrl: Fail probe of lpc-ctrl if reserved memory is not alignedAndrew Jeffery1-0/+13
Alignment is a hardware constraint of the LPC2AHB bridge, and misaligned reserved memory will present as corrupted data. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20191016233950.10100-1-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-09-25soc: aspeed: lpc: Add AST2600 compatible stringsBrad Bishop2-0/+3
The AST2600 has the same lpc-ctrl and lpc-snoop devices as the AST2500. Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190925125610.12096-4-bradleyb@fuzziesquirrel.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-09-25soc: aspeed: Add soc info driverJoel Stanley3-0/+141
This adds a SOC_BUS info driver for the ASPEED platform. The full ID table is preserved in this commit message in case someone finds a need to change the implemntation in the future. { "AST1100-A0", 0x00000200 }, { "AST1100-A1", 0x00000201 }, { "AST1100-A2", 0x00000202 }, { "AST1100-A3", 0x00000202 }, { "AST2050-A0", 0x00000200 }, { "AST2050-A1", 0x00000201 }, { "AST2050-A2", 0x00000202 }, { "AST2050-A3", 0x00000202 }, { "AST2100-A0", 0x00000300 }, { "AST2100-A1", 0x00000301 }, { "AST2100-A2", 0x00000302 }, { "AST2100-A3", 0x00000302 }, { "AST2150-A0", 0x00000202 }, { "AST2150-A1", 0x00000202 }, { "AST2200-A0", 0x00000102 }, { "AST2200-A1", 0x00000102 }, { "AST2300-A0", 0x01000003 }, { "AST2300-A1", 0x01010303 }, { "AST1300-A1", 0x01010003 }, { "AST1050-A1", 0x01010203 }, { "AST2400-A0", 0x02000303 }, { "AST2400-A1", 0x02010303 }, { "AST1400-A1", 0x02010103 }, { "AST1250-A1", 0x02010303 }, { "AST2500-A0", 0x04000303 }, { "AST2510-A0", 0x04000103 }, { "AST2520-A0", 0x04000203 }, { "AST2530-A0", 0x04000403 }, { "AST2500-A1", 0x04010303 }, { "AST2510-A1", 0x04010103 }, { "AST2520-A1", 0x04010203 }, { "AST2530-A1", 0x04010403 }, { "AST2500-A2", 0x04030303 }, { "AST2510-A2", 0x04030103 }, { "AST2520-A2", 0x04030203 }, { "AST2530-A2", 0x04030403 }, { "AST2600-A0", 0x05000303 }, { "AST2600-A1", 0x05010303 }, { "AST2600-A2", 0x05020303 }, { "AST2620-A1", 0x05010203 }, { "AST2620-A2", 0x05020203 }, Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20200921091644.133107-3-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-09-24soc: amlogic: pm-domains: use always-on flagKevin Hilman2-4/+4
Rather than use a governor to keep these domains always-on, instead use the flag GENPD_FLAG_ALWAYS_ON. This has the same effect, but with much lower overhead since the governor path is not used at all. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200921222135.7145-1-khilman@baylibre.com
2020-09-22soc: fsl: qe: Remove unnessesary check in ucc_set_tdm_rxtx_clkWang Hai1-1/+1
Fix smatch warning: drivers/soc/fsl/qe/ucc.c:526 ucc_set_tdm_rxtx_clk() warn: unsigned 'tdm_num' is never less than zero. 'tdm_num' is u32 type, never less than zero. Signed-off-by: Wang Hai <wanghai38@huawei.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2020-09-22soc: fsl: qman: convert to use be32_add_cpu()Liu Shixin1-1/+1
Signed-off-by: Liu Shixin <liushixin2@huawei.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2020-09-22soc: fsl: dpio: remove set but not used 'addr_cena'Jason Yan1-2/+0
This addresses the following gcc warning with "make W=1": drivers/soc/fsl/dpio/qbman-portal.c: In function ‘qbman_swp_enqueue_multiple_direct’: drivers/soc/fsl/dpio/qbman-portal.c:650:11: warning: variable ‘addr_cena’ set but not used [-Wunused-but-set-variable] 650 | uint64_t addr_cena; | ^~~~~~~~~ Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2020-09-22soc: fsl: qbman: Fix return value on successKrzysztof Kozlowski1-1/+1
On error the function was meant to return -ERRNO. This also fixes compile warning: drivers/soc/fsl/qbman/bman.c:640:6: warning: variable 'err' set but not used [-Wunused-but-set-variable] Fixes: 0505d00c8dba ("soc/fsl/qbman: Cleanup buffer pools if BMan was initialized prior to bootup") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2020-09-22soc: actions: include header to fix missing prototypeKrzysztof Kozlowski1-0/+1
Include the header with prototype of owl_sps_set_pg to fix: drivers/soc/actions/owl-sps-helper.c:16:5: warning: no previous prototype for 'owl_sps_set_pg' [-Wmissing-prototypes] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-09-21soc: aspeed: Improve kconfigJoel Stanley2-17/+21
Reword the kconfig text to be consistent and reflect that most drivers are available for all supported ASPEED chips (2400, 2500 and 2600). Rearrange the symbols the SoC drivers depend on so the menu doesn't appear unless you are building for ASPEED for compile testing. The SYSCON_MFD and REGMAP options are usually selected by drivers that need them, so do this. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20200916125731.784527-1-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-09-20soc: ti: Convert to DEFINE_SHOW_ATTRIBUTEQinglang Miao2-25/+5
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-18soc: amlogic: meson-ee-pwrc: add support for the Meson AXG SoCsNeil Armstrong1-0/+26
The Power Controller in the Amlogic AXG SoCs is similar to the GXL one but with less VPU memory domains to enable and a supplementary Audio memory power domain. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20200917064702.1459-3-narmstrong@baylibre.com
2020-09-18arm64: tegra: Initial Tegra234 VDK supportThierry Reding1-0/+10
The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It supports a subset of the peripherals that will be available in the final chip and serves as a bootstrapping platform. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18soc/tegra: pmc: Add Tegra234 supportThierry Reding1-0/+68
The PMC block is largely similar to that found on earlier chips, but not completely compatible. Allow binding to the instantiation found on Tegra234. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18soc/tegra: pmc: Reorder reset sources/levels definitionsThierry Reding1-39/+39
Move the definitions of reset sources and levels into a more natural location. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18soc/tegra: misc: Add Tegra234 supportThierry Reding1-0/+1
The MISC block is largely similar to that found on earlier chips, but not completely compatible. Allow binding to the instantiation found on Tegra234. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18soc/tegra: fuse: Add Tegra234 supportThierry Reding4-2/+45
Add support for FUSE block found on the Tegra234 SoC, which is largely similar to the IP found on previous generations. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18soc/tegra: fuse: Implement tegra_is_silicon()Thierry Reding1-0/+19
This function can be used by drivers to determine whether code is running on silicon or on a simulation platform. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18soc/tegra: fuse: Extract tegra_get_platform()Thierry Reding2-1/+6
This function extracts the PRE_SI_PLATFORM field from the HIDREV register and can be used to determine which platform the kernel runs on (silicon, simulation, ...). Note that while only Tegra194 and later define this field, it should be safe to call this on prior generations as well since this field should read as 0, indicating silicon. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-17soc: qcom: llcc: use devm_platform_ioremap_resource_byname()Qilong Zhang1-6/+1
Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Link: https://lore.kernel.org/r/20200916111517.99670-1-zhangqilong3@huawei.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-16soc: renesas: r8a779a0-sysc: Add r8a779a0 supportYoshihiro Shimoda3-0/+453
Add support for R-Car V3U (R8A779A0) SoC power areas and register access, because register specification differs from R-Car Gen2/3. Inspired by patches in the BSP by Tho Vu. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599810232-29035-5-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-15soc: qcom: apr: Fixup the error displayed on lookup failureSibi Sankar1-1/+1
APR client incorrectly prints out "ret" variable on pdr_add_lookup failure, it should be printing the error value returned by the lookup instead. Fixes: 8347356626028 ("soc: qcom: apr: Add avs/audio tracking functionality") Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200915154232.27523-1-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-14soc: qcom: pdr: Fixup array type of get_domain_list_resp messageSibi Sankar1-1/+1
The array type of get_domain_list_resp is incorrectly marked as NO_ARRAY. Due to which the following error was observed when using pdr helpers with the downstream proprietary pd-mapper. Fix this up by marking it as VAR_LEN_ARRAY instead. Err logs: qmi_decode_struct_elem: Fault in decoding: dl(2), db(27), tl(160), i(1), el(1) failed to decode incoming message PDR: tms/servreg get domain list txn wait failed: -14 PDR: service lookup for tms/servreg failed: -14 Tested-by: Rishabh Bhatnagar <rishabhb@codeaurora.org> Fixes: fbe639b44a82 ("soc: qcom: Introduce Protection Domain Restart helpers") Reported-by: Rishabh Bhatnagar <rishabhb@codeaurora.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200914145807.1224-1-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-14soc: qcom: socinfo: Add msm8992/4 and apq8094 SoC IDsKonrad Dybcio1-0/+3
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200602201229.322578-1-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13Merge tag 'arm-soc/for-5.10/drivers' of https://github.com/Broadcom/stblinux into arm/driversOlof Johansson6-10/+498
This pull request contains Broadcom SoCs drivers changes for 5.10, please pull the following: - Alvaro adds support for the BCM63xx (DSL) SoCs power domain controller and adds support for the 6318, 6328, 6362, 63268. - Florian adds support for tuning the Bus Interface Unit on 72164 and 72165, enables the Brahma-B53 and Cortex-A72 read-ahead cache for the 64-bit capable ARCH_BRCMSTB platforms, and finally updates the GISB driver to support breakpoint notifications. * tag 'arm-soc/for-5.10/drivers' of https://github.com/Broadcom/stblinux: bus: brcmstb_gisb: Add support for breakpoint interrupts dt-bindings: bus: Document breakpoint interrupt for gisb-arb soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2 soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165 soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164 MIPS: BMIPS: dts: add BCM63268 power domain support MIPS: BMIPS: dts: add BCM6362 power domain support MIPS: BMIPS: dts: add BCM6328 power domain support soc: bcm: add BCM63xx power domain driver MIPS: BMIPS: add BCM6318 power domain definitions MIPS: BMIPS: add BCM63268 power domain definitions MIPS: BMIPS: add BCM6362 power domain definitions MIPS: BMIPS: add BCM6328 power domain definitions dt-bindings: soc: brcm: add BCM63xx power domain binding soc: bcm: brcmstb: biuctrl: Enable Read-ahead cache bus: brcmstb_gisb: Shorten prints Link: https://lore.kernel.org/r/20200912032153.1216354-3-f.fainelli@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-09-13Merge tag 'omap-for-v5.10/ti-sysc-drop-pdata-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/socOlof Johansson2-8/+313
Add initial genpd support for omaps to drop more platform data We now drop legacy platform data for RTC on am3, am4 and dra7. And we add initial genpd support for PRM (Power and Reset Manager) and use it to drop legacy platform data for am3 sgx and omap4/5 l4_abe interconnect instance. * tag 'omap-for-v5.10/ti-sysc-drop-pdata-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: Drop legacy platform data for dra7 rtcss ARM: OMAP2+: Drop legacy platform data for am3 and am4 rtc soc: ti: pm33xx: Simplify RTC usage to prepare to drop platform data ARM: dts: Configure omap4 and 5 l4_abe for genpd and drop platform data ARM: dts: Configure am3 and am4 sgx for genpd and drop platform data soc: ti: omap-prm: Configure omap4 and 5 l4_abe power domain soc: ti: omap-prm: Configure sgx power domain for am3 and am4 soc: ti: omap-prm: Add basic power domain support dt-bindings: omap: Update PRM binding for genpd Link: https://lore.kernel.org/r/pull-1599132307-761202@atomide.com-2 Signed-off-by: Olof Johansson <olof@lixom.net>
2020-09-13Merge tag 'versatile-soc-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into arm/socOlof Johansson1-1/+1
Versatile SoC updates for the v5.10 kernel cycle: - Drop a static qualifier in integrator_soc_init() - Remove Integrator and Versatile from PHYS_OFFSET * tag 'versatile-soc-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: versatile: Remove Integrator and Realview from PHYS_OFFSET soc: integrator: Drop pointless static qualifier in integrator_soc_init() Link: https://lore.kernel.org/r/CACRpkdYYDSg8FAjJAqew5yEu7H1Y3E1rPN9TL25K31T=QWATuA@mail.gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-09-13Merge tag 'samsung-soc-s3c-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/socOlof Johansson4-1/+362
Samsung S3C24xx and S3C64xx machine code cleanup for v5.10 Big cleanup for the Samsung S3C24xx and S3C64xx platforms, although it also touches files shared with S5Pv210 and Exynos. This is mostly Arnd Bergmann work which Krzysztof Kozlowski took over, rebased and polished. The goal is to cleanup, merge and finally make the Samsung S3C24xx and S3C64xx architectures multiplatform. The multiplatform did not happen yet here - just cleaning up and merging into one arch/arm/mach-s3c directory. However this is step forward for multiplatform or at least to keep this code still maintainable. This pulls also branch with changes for Samsung SoC sound drivers from broonie/sound because the cleanups there were part of this series and all further patches depend on them. * tag 'samsung-soc-s3c-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (62 commits) ARM: s3c: Avoid naming clash of S3C24xx and S3C64xx timer setup ARM: s3c: Cleanup from old plat-samsung include ARM: s3c: make headers local if possible ARM: s3c: move into a common directory ARM: s3c24xx: stop including mach/hardware.h from mach/io.h cpufreq: s3c24xx: move low-level clk reg access into platform code cpufreq: s3c2412: use global s3c2412_cpufreq_setrefresh ARM: s3c: remove cpufreq header dependencies cpufreq: s3c24xx: split out registers fbdev: s3c2410fb: remove mach header dependency ARM: s3c24xx: bast: avoid irq_desc array usage ARM: s3c24xx: spi: avoid hardcoding fiq number in driver ARM: s3c24xx: include mach/irqs.h where needed ARM: s3c24xx: move s3cmci pinctrl handling into board files ARM: s3c24xx: move iis pinctrl config into boards ARM: s3c24xx: move spi fiq handler into platform ARM: s3c: adc: move header to linux/soc/samsung ARM: s3c24xx: move irqchip driver back into platform ARM: s3c24xx: move regs-spi.h into spi driver ARM: s3c64xx: remove mach/hardware.h ... Link: https://lore.kernel.org/r/20200831154751.7551-1-krzk@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2020-09-11soc: ti: k3-socinfo: Add entry for J7200Peter Ujfalusi1-0/+1
Update K3 chipinfo driver to support new TI J7200 SoC. It's JTAG PARTNO is 0xBB6D. Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11soc: ti: pruss: support CORECLK_MUX and IEPCLK_MUXGrzegorz Jaszczyk1-7/+177
The IEPCLK_MUX is present on all SoCs whereas the CORECLK_MUX is present only on AM65x SoCs and J721E. Add support for both these CLK muxes. This allows the clock rates and clock parents for these to be controlled through DT leveraging the clk infrastructure for configuring the default parents and rates. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11soc: ti: ti_sci_pm_domains: switch to use multiple genpds instead of oneTero Kristo1-130/+121
Current implementation of the genpd support over TI SCI uses a single genpd across the whole SoC, and attaches multiple devices to this. This solution has its drawbacks, like it is currently impossible to attach more than one power domain to a device; the core genpd implementation requires one genpd per power-domain entry in DT for a single device. Also, some devices like USB apparently require their own genpd during probe time, the current shared approach in use does not work at all. Switch the implementation over to use a single genpd per power domain entry in DT. The domains are registered with the onecell approach, but we also add our own xlate service due to recent introduction of the extended flag for TI SCI PM domains; genpd core xlate service requires a single cell per powerdomain, but we are using two cells. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11soc: ti: pruss: Enable support for ICSSG subsystems on K3 J721E SoCsSuman Anna1-0/+1
The K3 J721E family of SoCs have a revised version of the PRU-ICSS (ICSSG) processor subsystem present on K3 AM65x SoCs. These SoCs contain typically two ICSSG instances named ICSSG0 and ICSSG1. The two ICSSGs are identical to each other for the most part with minor SoC integration differences and capabilities. The ICSSG1 supports slightly enhanced features like SGMII mode Ethernet, while the ICSSG0 instance is limited to MII mode only. There is no change in the Interrupt Controller w.r.t AM65x. All other integration aspects are very similar to the ICSSGs on AM65x SoCs. The existing pruss platform driver has been updated to support these new ICSSG instances through new J721E specific compatibles. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11soc: ti: pruss: Enable support for ICSSG subsystems on K3 AM65x SoCsSuman Anna2-1/+2
The K3 AM65x family of SoCs have the next generation of the PRU-ICSS processor subsystem capable of supporting Gigabit Ethernet, and is commonly referred to as ICSSG. These SoCs contain typically three ICSSG instances named ICSSG0, ICSSG1 and ICSSG2. The three ICSSGs are identical to each other for the most part with minor SoC integration differences and capabilities. The ICSSG2 supports slightly enhanced features like SGMII mode Ethernet, while the ICSS0 and ICSSG1 instances are limited to MII mode only. The ICSSGs on K3 AM65x SoCs are in general super-sets of the PRUSS on the AM57xx/66AK2G SoCs. They include two additional auxiliary PRU cores called RTUs and few other additional sub-modules. The interrupt integration is also different on the K3 AM65x SoCs and are propagated through various SoC-level Interrupt Router and Interrupt Aggregator blocks. Other IP level differences include different constant tables, differences in system event interrupt input sources etc. They also do not have a programmable module reset line like those present on AM33xx/AM43xx SoCs. The modules are reset just like any other IP with the SoC's global cold/warm resets. The existing pruss platform driver has been updated to support these new ICSSG instances through new AM65x specific compatibles. A build dependency with ARCH_K3 is added to enable building all the existing PRUSS platform drivers for this ARMv8 platform. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11soc: ti: pruss: Add support for PRU-ICSS subsystems on 66AK2G SoCSuman Anna2-1/+2
The 66AK2G SoC supports two PRU-ICSS instances, named PRUSS0 and PRUSS1, each of which has two PRU processor cores. The two PRU-ICSS instances are identical to each other with few minor SoC integration differences, and are very similar to the PRU-ICSS1 of AM57xx/AM43xx. The Shared Data RAM size is larger and the number of interrupts coming into MPU INTC is like the instances on AM437x. There are also few other differences attributing to integration in Keystone architecture (like no SYSCFG register or PRCM handshake protocols). Other IP level differences include different constant table, differences in system event interrupt input sources etc. They also do not have a programmable module reset line like those present on AM33xx/AM43xx SoCs. The modules are reset just like any other IP with the SoC's global cold/warm resets. The existing PRUSS platform driver has been enhanced to support these 66AK2G PRU-ICSS instances through new 66AK2G specific compatible for properly probing and booting all the different PRU cores in each PRU-ICSS processor subsystem. A build dependency with ARCH_KEYSTONE is added to enable the driver to be built in K2G-only configuration. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11soc: ti: pruss: Add support for PRU-ICSS subsystems on AM57xx SoCsSuman Anna2-1/+2
The AM57xx family of SoCs supports two PRU-ICSS instances, each of which has two PRU processor cores. The two PRU-ICSS instances are identical to each other, and are very similar to the PRU-ICSS1 of AM33xx/AM43xx except for a few minor differences like the RAM sizes and the number of interrupts coming into the MPU INTC. They do not have a programmable module reset line unlike those present on AM33xx/AM43xx SoCs. The modules are reset just like any other IP with the SoC's global cold/warm resets. Each PRU-ICSS's INTC is also preceded by a Crossbar that enables multiple external events to be routed to a specific number of input interrupt events. Any interrupt event directed towards PRUSS needs this crossbar to be setup properly on the firmware side. The existing PRUSS platform driver has been enhanced to support these AM57xx PRU-ICSS instances through new AM57xx specific compatible for properly probing and booting all the different PRU cores in each PRU-ICSS processor subsystem. A build dependency with SOC_DRA7XX is also added to enable the driver to be built in AM57xx-only configuration (there is no separate Kconfig option for AM57xx vs DRA7xx). Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11soc: ti: pruss: Add support for PRU-ICSSs on AM437x SoCsSuman Anna2-2/+35
The AM437x SoCs have two different PRU-ICSS subsystems: PRU-ICSS1 and a smaller PRU-ICSS0. Enhance the PRUSS platform driver to support both the PRU-ICSS sub-systems on these SoCs. The PRU-ICSS1 on AM437x is very similar to the PRU-ICSS on AM33xx except for few minor differences - increased Instruction RAM, increased Shared Data RAM2, and 1 less interrupt (PRUSS host interrupt 7 which is redirected to the other PRUSS) towards the MPU INTC. The PRU-ICSS0 is a cut-down version of the IP, with less DRAM per PRU, no Shared DRAM etc. It also does not have direct access to L3 bus regions, there is a single interface to L3 for both PRUSS0 and PRUSS1, and it would have to go through the PRUSS1's interface. The PRUSS_SYSCFG register is reserved on PRUSS0, so any external access requires the programming the corresponding PRUSS_SYSCFG register in PRUSS1. It does have its own dedicated I/O lines though. Note that this instance does not support any PRU Ethernet related use cases. The adaptation uses SoC-specific compatibles in the driver and uses a newly introduced pruss_match_private_data structure and the pruss_get_private_data() function to retrieve a PRUSS instance specific data using a device-name based lookup logic. The reset and the L3 external access are managed by the parent interconnect ti-sysc bus driver so that PRUSS1 and PRUSS0 can be independently supported. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11soc: ti: pruss: Add a platform driver for PRUSS in TI SoCsSuman Anna3-0/+159
The Programmable Real-Time Unit - Industrial Communication Subsystem (PRU-ICSS) is present on various TI SoCs such as AM335x or AM437x or the Keystone 66AK2G. Each SoC can have one or more PRUSS instances that may or may not be identical. For example, AM335x SoCs have a single PRUSS, while AM437x has two PRUSS instances PRUSS1 and PRUSS0, with the PRUSS0 being a cut-down version of the PRUSS1. The PRUSS consists of dual 32-bit RISC cores called the Programmable Real-Time Units (PRUs), some shared, data and instruction memories, some internal peripheral modules, and an interrupt controller. The programmable nature of the PRUs provide flexibility to implement custom peripheral interfaces, fast real-time responses, or specialized data handling. The PRU-ICSS functionality is achieved through three different platform drivers addressing a specific portion of the PRUSS. Some sub-modules of the PRU-ICSS IP reuse some of the existing drivers (like davinci mdio driver or the generic syscon driver). This design provides flexibility in representing the different modules of PRUSS accordingly, and at the same time allowing the PRUSS driver to add some instance specific configuration within an SoC. The PRUSS platform driver deals with the overall PRUSS and is used for managing the subsystem level resources like various memories and the CFG module. It is responsible for the creation and deletion of the platform devices for the child PRU devices and other child devices (like Interrupt Controller, MDIO node and some syscon nodes) so that they can be managed by specific platform drivers. The PRUSS interrupt controller is managed by an irqchip driver, while the individual PRU RISC cores are managed by a PRU remoteproc driver. The driver currently supports the AM335x SoC, and support for other TI SoCs will be added in subsequent patches. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11soc: ti: k3: ringacc: add am65x sr2.0 supportGrygorii Strashko1-3/+30
The AM65x SR2.0 Ringacc has fixed errata i2023 "RINGACC, UDMA: RINGACC and UDMA Ring State Interoperability Issue after Channel Teardown". This errata also fixed for J271E SoC. Use SOC bus data for K3 SoC identification and enable i2023 errate w/a only for the AM65x SR1.0. This also makes obsolete "ti,dma-ring-reset-quirk" DT property. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
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