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path: root/drivers/spmi/spmi-pmic-arb.c (follow)
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2015-03-26spmi: pmic_arb: add support for hw version 2Gilad Avidov1-59/+260
Qualcomm PMIC Arbiter version-2 changes from version-1 are: - Some different register offsets. - New channel register space, one per PMIC peripheral (ppid). All tx traffic uses these channels. - New observer register space. All rx trafic uses this space. - Different command format for spmi command registers. Reviewed-by: Sagar Dharia <sdharia@codeaurora.org> Signed-off-by: Gilad Avidov <gavidov@codeaurora.org> Tested-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-10-20spmi: drop owner assignment from platform_driversWolfram Sang1-1/+0
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-02-15spmi: pmic_arb: add support for interrupt handlingJosh Cartwright1-2/+375
The Qualcomm PMIC Arbiter, in addition to being a basic SPMI controller, also implements interrupt handling for slave devices. Note, this is outside the scope of SPMI, as SPMI leaves interrupt handling completely unspecified. Extend the driver to provide a irq_chip implementation and chained irq handling which allows for these interrupts to be used. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-02-15spmi: Add MSM PMIC Arbiter SPMI controllerKenneth Heitke1-0/+405
Qualcomm's PMIC Arbiter SPMI controller functions as a bus master and is used to communication with one or more PMIC (slave) devices on the SPMI bus. The PMIC Arbiter is actually a hardware wrapper around the SPMI controller that provides concurrent and autonomous PMIC access to various entities that need to communicate with the PMIC. The SPMI controller hardware handles all of the SPMI bus activity (bus arbitration, sequence start condition, transmission of frames, etc). This software driver uses the PMIC Arbiter register interface to initiate command sequences on the SPMI bus. The status register is read to determine when the command sequence has completed and whether or not it completed successfully. Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org> Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>