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2018-11-20staging: axis-fifo: Split line to stay in 80 characters.Cristian Sicilia1-1/+2
The line is split up to stay in 80 characters- Signed-off-by: Cristian Sicilia <sicilia.cristian@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-10-09staging: axis-fifo: remove duplicated include from axis-fifo.cYueHaibing1-2/+0
Remove duplicated include. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-10-09staging: axis-fifo: Remove parentheses in axis-fifo.cIoannis Valasakis1-10/+10
staging: axis-fifo: remove parentheses in axis-fifo.c Remove parentheses from the end of line and conform to the coding style guidelines. Reported by checkpatch. Add an extra space to the function arguments to fix indentation. Signed-off-by: Ioannis Valasakis <code@wizofe.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-10-02staging: axis-fifo: add error handling of class_create()Alexey Khoroshilov1-0/+2
Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-29staging: fix platform_no_drv_owner.cocci warningskbuild test robot1-1/+0
drivers/staging/axis-fifo/axis-fifo.c:1081:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Fixes: 4a965c5f89de ("staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core") CC: Jacob Feder <jacobsfeder@gmail.com> Signed-off-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-28staging: axis-fifo: fix return value check in axis_fifo_probe()Wei Yongjun1-2/+2
In case of error, the function device_create() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Fixes: 4a965c5f89de ("staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-24staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP coreJacob Feder5-0/+1207
This IP core has read and write AXI-Stream FIFOs, the contents of which can be accessed from the AXI4 memory-mapped interface. This is useful for transferring data from a processor into the FPGA fabric. The driver creates a character device that can be read/written to with standard open/read/write/close. See Xilinx PG080 document for IP details. https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf The driver currently supports only store-forward mode with a 32-bit AXI4 Lite interface. DOES NOT support: - cut-through mode - AXI4 (non-lite) Signed-off-by: Jacob Feder <jacobsfeder@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>