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2021-09-29drm/i915: constify color function vtable.Dave Airlie2-47/+93
This clarifies quite well what functions get used on what platforms instead of having to decipher the old tree. v2: fixed IVB mistake (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/49e46e61206d4fdcf08fb5dc1978da3fce702134.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915: constify hotplug function vtable.Dave Airlie3-10/+24
Use a macro to avoid mistakes, this type of macro is only used in a couple of places. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/af229c1e8ec894f177b344ab77b90e32c33428de.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915: constify fdi link training vtableDave Airlie2-5/+17
Put the vtable into ro memory. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ec4687956f9b98024fea55b2f0ed1e192e244ff1.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915: split the dpll clock compute out from display vtable.Dave Airlie3-12/+18
this single function might be possible to merge later, but for now it's simple to just split it out. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ba570aa10b694b2e8640e0c58430fd0053c306b7.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915: split fdi link training from display vtable.Dave Airlie2-7/+12
It may make sense to merge this with display again later, however the fdi use of the vtable is limited to only a few generations. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/7af7359b6cec33bd2d32152893d9a1e8f8cf7f21.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915: split irq hotplug function from display vtableDave Airlie3-10/+17
This provide a service from irq to display, so make it separate Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/05f533064709764dff8bcfef6a58f9a8482dc5bb.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915: split cdclk functions from display vtable.Dave Airlie2-72/+78
This moves all the cdclk related functions into their own vtable. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/591b7b6a79c4ab644a161ae00b7d630b3ef16434.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915: split audio functions from display vtableDave Airlie2-18/+25
These are only used internally in the audio code Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d12257cc7685a9b52618f7da444ba1fc8848b4db.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915: split color functions from display vtableDave Airlie2-49/+54
These are only used internally in the color module Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/084a31362f1621d2f556069bb2bc47d362a63823.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915: split watermark vfuncs from display vtable.Dave Airlie3-45/+53
These are the watermark api between display and pm. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/7130356324ef3de59b4e913f025d7dce822157ee.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915: split clock gating init from display vtableDave Airlie2-25/+32
This function is only used inside intel_pm.c Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/95d626a7329ab5779804762894e304e12c6dbe1f.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915/display: add intel_fdi_link_train wrapper.Dave Airlie3-1/+11
This wraps the fdi link training vfunc to make it clearer. Suggested by Jani. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1bb978bcb6f16fbdaf08f2800a179b774525b59e.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915: add wrappers around cdclk vtable funcs.Dave Airlie4-11/+44
This adds wrappers around all the vtable callers so they are in one place. Suggested by Jani. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c3dd7aaad039e76acde9dda7211468907aa657c0.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915/wm: provide wrappers around watermark vfuncs calls (v3)Dave Airlie3-102/+123
This moves one wrapper from the pm->display side, and creates wrappers for all the others, this should simplify things later. One thing to note is that the code checks the existence of some of these ptrs, so the wrappers are a bit complicated by that. Suggested by Jani. v2: fixup warnings in wrong place error. v3 by Jani: fix intel_compute_global_watermarks() return value check Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ee2760c45896568c9dd9114a575509619bd44ef2.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915: make update_wm take a dev_priv.Dave Airlie4-20/+14
The crtc was never being used here. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/70438bface47fa683cda8a9e95d0556fca448172.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915/pm: drop get_fifo_size vfunc.Dave Airlie2-11/+11
The i845_update_wm code was always calling the i845 variant, and the i9xx_update_wm had only a choice between i830 and i9xx paths, hardly worth the vfunc overhead. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/07523b1e46cd10adb2991ed4d2619b542a48c1ce.1632869550.git.jani.nikula@intel.com
2021-09-29drm/i915/uncore: split the fw get function into separate vfuncDave Airlie2-34/+43
constify it while here. drop the put function since it was never overloaded and always has done the same thing, no point in indirecting it for show. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/41c3e1896162fc08e22e40b00642791365a8c00e.1632869550.git.jani.nikula@intel.com
2021-09-28drm/i915/display: Fix the dsc check while selecting min_cdclkVandita Kulkarni1-6/+4
The right parameter that selects second dsc engine is dsc_split. Hence use dsc_split instead of slice_count while selecting the cdclk in order to accommodate 1ppc limitaion of vdsc. Fixes: fe01883fdcef ("drm/i915: Get proper min cdclk if vDSC enabled") Suggested-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210915054338.29869-1-vandita.kulkarni@intel.com
2021-09-27drm/i915/audio: Use BIOS provided value for RKL HDA linkKai-Heng Feng1-2/+3
Commit 989634fb49ad ("drm/i915/audio: set HDA link parameters in driver") makes HDMI audio on Lenovo P350 disappear. So in addition to TGL, extend the logic to RKL to use BIOS provided value to fix the regression. Fixes: 989634fb49ad ("drm/i915/audio: set HDA link parameters in driver") Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210906041300.508458-1-kai.heng.feng@canonical.com
2021-09-24drm/i915/fbc: Allow higher compression limits on FBC1Ville Syrjälä1-13/+7
On FBC1 we can specify an arbitrary cfb stride. The hw will simply throw away any compressed line that would exceed the specified limit and keep using the uncompressed data instead. Thus we can allow arbitrary compression limits. The one thing we have to keep in mind though is that the cfb stride is specified in units of 32B (gen2) or 64B (gen3+). Fortunately X-tile is already 128B (gen2) or 512B (gen3+) wide so as long as we limit outselves to the same 4x compression limit that FBC2 has we are guaranteed to have a sufficiently aligned cfb stride. Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210921152517.803-5-ville.syrjala@linux.intel.com
2021-09-24drm/i915/fbc: Implement Wa_16011863758 for icl+Ville Syrjälä1-2/+10
There's some kind of weird corner cases in FBC which requires FBC segments to be separated by at least one extra cacheline. Make sure that is present. v2: Respin to fit in with skl_fbc_min_cfb_stride() v3: Make it build Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210921181245.15091-1-ville.syrjala@linux.intel.com
2021-09-24drm/i915/fbc: Align FBC segments to 512B on glk+Ville Syrjälä2-3/+15
Apply the same 512 byte FBC segment alignment to glk+ as we use on skl+. The only real difference is that we now have a dedicated register for the FBC override stride. Not 100% sure which platforms really need the 512B alignment, but it's easiest to just do it on everything. Also the hardware no longer seems to misclaculate the CFB stride for linear, so we can omit the use of the override stride for linear unless the stride is misaligned. Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210921152517.803-3-ville.syrjala@linux.intel.com
2021-09-24drm/i915/fbc: Rework cfb stride/size calculationsVille Syrjälä2-61/+123
The code to calculate the cfb stride/size is a bit of mess. The cfb size is getting calculated based purely on the plane stride and plane height. That doesn't account for extra alignment we want for the cfb stride. The gen9 override stride OTOH is just calculated based on the plane width, and it does try to make things more aligned but any extra alignment added there is not considered in the cfb size calculations. So not at all convinced this is working as intended. Additionally the compression limit handling is split between the cfb allocation code and g4x_dpfc_ctl_limit() (for the 16bpp case), which is just confusing. Let's streamline the whole thing: - Start with the plane stride, convert that into cfb stride (cfb is always 4 bytes per pixel). All the calculations will assume 1:1 compression limit since that will give us the max values, and we don't yet know how much stolen memory we will be able to allocate - Align the cfb stride to 512 bytes on modern platforms. This guarantees the 4 line segment will be 512 byte aligned regardles of the final compression limit we choose later. The 512 byte alignment for the segment is required by at least some of the platforms, and just doing it always seems like the easiest option - Figure out if we need to use the override stride or not. For X-tiled it's never needed since the plane stride is already 512 byte aligned, for Y-tiled it will be needed if the plane stride is not a multiple of 512 bytes, and for linear it's apparently always needed because the hardware miscalculates the cfb stride as PLANE_STRIDE*512 instead of the PLANE_STRIDE*64 that it use with linear. - The cfb size will be calculated based on the aligned cfb stride to guarantee we actually reserved enough stolen memory and the FBC hw won't end up scribbling over whatever else is allocated in stolen - The compression limit handling we just do fully in the cfb allocation code to make things less confusing v2: Write the min cfb segment stride calculation in a more explicit way to make it clear what is going on v3: Remeber to update fbc->limit when changing to 16bpp Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v2 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210923042151.19052-1-ville.syrjala@linux.intel.com
2021-09-23drm/i915: Fix HPLL watermark readout for g4xVille Syrjälä1-2/+5
If HPLL watermarks are already enabled, let's not mark them as disabled by forgetting to bump 'level' before we call g4x_raw_plane_wm_set(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514125751.17075-6-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
2021-09-23drm/i915/display: Only keep PSR enabled if there is active planesJosé Roberto de Souza7-80/+98
PSR always had a requirement to only be enabled if there is active planes but not following that never caused any issues. But that changes in Alderlake-P, leaving PSR enabled without active planes causes transcoder/port underruns. Similar behavior was fixed during the pipe disable sequence by commit 84030adb9e27 ("drm/i915/display: Disable audio, DRRS and PSR before planes"). intel_dp_compute_psr_vsc_sdp() had to move from intel_psr_enable_locked() to intel_psr_compute_config() because we need to be able to disable/enable PSR from atomic states without connector and encoder state. Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210922215242.66683-3-jose.souza@intel.com
2021-09-23drm/i915/display: Match PSR2 selective fetch sequences with specificationJosé Roberto de Souza5-19/+36
We were not completely following the selective fetch programming sequence, here some things we were doing wrong: - not programming plane selective fetch a PSR2_MAN_TRK_CTL registers when doing a modeset - programming PSR2_MAN_TRK_CTL out of vblank With this changes the last remainig underrun found in Alderlake-P is fixed. Bspec: 55229 Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210922215242.66683-2-jose.souza@intel.com
2021-09-23drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware loadJosé Roberto de Souza1-13/+3
Specification asks for DC_STATE_DEBUG_MASK_CORES to be set for all platforms that supports DMC, not only for geminilake and broxton. While at is also taking the oportunity to simply the code. BSpec: 7402 BSpec: 49436 Reviewed-by: Imre Deak <imre.deak@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210922215242.66683-1-jose.souza@intel.com
2021-09-23drm/i915/adlp: Add support for remapping CCS FBsImre Deak5-47/+89
Add support for remapping CCS FBs on ADL-P to remove the restriction of the power-of-two sized stride and the 2MB surface offset alignment for these FBs. We can only remap the tiles on the main surface, not the tiles on the CCS surface, so userspace has to generate the CCS surface aligning to the POT size padded main surface stride (by programming the AUX pagetable accordingly). For the required AUX pagetable setup, this requires that either the main surface stride is 8 tiles or that the stride is 16 tiles aligned (= 64 kbytes, the area mapped by one AUX PTE). v2: - Init intel_remapped_info::plane_alignment only for remapped views and do this from intel_fb_view_init(). Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210906182715.3915100-6-imre.deak@intel.com
2021-09-23drm/i915: Follow a new->old platform check order in intel_fb_stride_alignmentImre Deak1-8/+8
Follow the usual new->old order in intel_fb_stride_alignment() platform check ladder. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210906182715.3915100-5-imre.deak@intel.com
2021-09-23drm/i915/adlp: Assert that VMAs in DPT start at 0Imre Deak1-0/+5
Atm the DPT object can accommodate only one VMA, so the VMA offset will be always 0. Add an assert for this. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210906182715.3915100-4-imre.deak@intel.com
2021-09-23drm/i915/adlp: Require always a power-of-two sized CCS surface strideImre Deak1-4/+30
At the moment CCS FB strides must be power-of-two sized, but a follow-up change will add support remapping these FBs, allowing the FB passed in by userspace to have a non-POT sized stride. For these remapped FBs we can only remap the main surface, not the CCS surface. This means that userspace has to always generate the CCS surface aligning to the POT stride padded main surface (by setting up the CCS AUX pagetables accordingly). Adjust the CCS surface stride check to enforce this. No functional change. v2: - Fix the gen12_ccs_aux_stride() is not static sparse warning. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210906182715.3915100-3-imre.deak@intel.com
2021-09-23drm/i915: Use tile block based dimensions for CCS origin x, y checkImre Deak1-5/+25
The tile size for all surface types is 4 kbyte (or 2 kbyte on old platforms), with the exception of the TGL/ADL CCS surface where the tile size is 64 bytes. To be able to remap CCS FBs the CCS surface tile needs to be defined as 4 kbyte as well (the granularity of GTT pages in a remapped view). The only place using the dimension of the 64 byte CCS area is the initial check for the main vs. CCS plane origin coordinate match. To prepare for adding support for remapping CCS FBs let's call the 64 byte CCS area a 'tile block' and add a helper to retrieve the dimensions for it. No functional change. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210906182715.3915100-2-imre.deak@intel.com
2021-09-22drm/i915: Apply WaUse32BppForSRWM to elk as well as ctgVille Syrjälä1-8/+4
The w/a database lists this for both ctg and elk. So let's apply it to elk as well. And add the w/a name. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514125751.17075-5-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
2021-09-22drm/i915: Fix g4x cxsr enable conditionVille Syrjälä1-3/+2
The intention was to check whether the primary plane is enabled without any sprites planes being enabled. Instead we ended up checking whether just any one of the planes is enabled. g4x isn't vlv/chv and cxsr only works with the primary plane. Fix the check to examine the bitmask of active planes rather than the number of bits set in said bitmask. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514125751.17075-3-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
2021-09-22drm/i915: Use u8 consistently for active_planes bitmaskVille Syrjälä1-3/+3
Be consistent in that active_planes bitmask fits in a u8. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514125751.17075-4-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
2021-09-22drm/i915: s/crtc_state/new_crtc_state/ etc.Ville Syrjälä1-19/+19
intel_plane_atomic_calc_changes() deals with both the old and new crtc/plane states. Make the variable names reflect that more clearly. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514125751.17075-2-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
2021-09-22drm/i915/display: Add HDR mode helper functionTejas Upadhyay1-3/+7
Add helper function with returns if HDR mode in on Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210907113658.1351456-1-tejaskumarx.surendrakumar.upadhyay@intel.com [vsyrjala: fix up alignment to match codingstyle] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2021-09-20drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132bJani Nikula1-0/+11
There's a new register pair for 128b/132b mode where you need to set the pixel clock in Hz. v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper Bspec: 54128 Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a2902cc188973f022f282f2a77e693afdecefb5a.1631191763.git.jani.nikula@intel.com
2021-09-20drm/i915/dg2: use 128b/132b transcoder DDI modeJani Nikula1-7/+20
128b/132b has a separate transcoder DDI mode, which also requires the MST transport select to be set. Note that we'll use DP MST also for single-stream 128b/132b. Having the FDI and 128b/132b modes share the register mode value complicates things a bit. v2: - Use HAS_DP20 abstraction for 128b/132b mode (Ville) - Use intel_dp_is_uhbr() helper Bspec: 50493 Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/279bfbd979e0256fae13a5231e07e2f4fb665c07.1631191763.git.jani.nikula@intel.com
2021-09-20drm/i915/dp: add HAS_DP20 macroJani Nikula1-0/+1
Let's abstract the DP 2.0 feature. Initially just DG2. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/3746e700641bc17eff270569387fe869707d92ed.1631191763.git.jani.nikula@intel.com
2021-09-20drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0Jani Nikula1-1/+16
Set the DP 2.0 128b/132b channel encoding for UHBR rates. v2: Fix UHBR port clock check, use intel_dp_is_uhbr() Bspec: 54128 Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c88b08d80a96d1229ae941b296590633be4d8711.1631191763.git.jani.nikula@intel.com
2021-09-20drm/i915/dp: select 128b/132b channel encoding for UHBR ratesJani Nikula1-1/+2
UHBR rates and 128b/132b channel encoding go hand in hand. v2: Fix check for >= UHBR rates using intel_dp_is_uhbr() (Ville) Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/b4ffd0187b306c0abaa08b89ed35c993ad8145c7.1631191763.git.jani.nikula@intel.com
2021-09-20drm/i915/dp: use 128b/132b TPS2 for UHBR+ link ratesJani Nikula1-3/+7
128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b TPS2 for channel equalization. v2: Use intel_dp_is_uhbr Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1 Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/723b29223dc570c8b63c3c6fe5fb772d9db06c0d.1631191763.git.jani.nikula@intel.com
2021-09-20drm/i915/dp: add helper for checking for UHBR link rateJani Nikula2-0/+7
Helpful abstraction to avoid duplication. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/fe9a222ad900da797c989de9f7fa13928d2c9861.1631191763.git.jani.nikula@intel.com
2021-09-20drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b modeJani Nikula2-4/+4
Unfortunately, the DP 2.0 128b/132b DDI mode selection in the register conflicts with FDI. Since we have to deal with both meanings in the same code, for different platforms, clarify the macro name so we don't forget. Bspec: 50493 Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/260e4da302d47ae50122eb8d517be6ac3ccb15f2.1631191763.git.jani.nikula@intel.com
2021-09-20drm/dp: add helper for extracting adjust 128b/132b TX FFE presetJani Nikula1-0/+14
The DP 2.0 128b/132b channel coding uses TX FFE presets instead of vswing and pre-emphasis. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4ba129c51aeb01a5f210de7026abe704a554a178.1631191763.git.jani.nikula@intel.com
2021-09-20drm/dp: use more of the extended receiver capJani Nikula1-1/+1
Extend the use of extended receiver cap at 0x2200 to cover MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides the DP 2.0 128b/132b channel encoding cap. v2: Extend to DP_RECEIVER_CAP_SIZE (Ville) Cc: Lyude Paul <lyude@redhat.com> Cc: dri-devel@lists.freedesktop.org Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/649051cb896821147feee91aab1f2abc523c1353.1631191763.git.jani.nikula@intel.com
2021-09-20drm/dp: add DP 2.0 UHBR link rate and bw code conversionsJani Nikula1-4/+22
The bw code equals link_rate / 0.27 Gbps only for 8b/10b link rates. Handle DP 2.0 UHBR rates as special cases, though this is not pretty. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/cab4edda8834d6b4db610fabb5e1f1f18ae33c2c.1631191763.git.jani.nikula@intel.com
2021-09-17drm/i915/display/adlp: Add new PSR2 workaroundsJosé Roberto de Souza2-1/+30
Wa_16014451276 fixes the starting coordinate for PSR2 selective updates. CHICKEN_TRANS definition of the workaround bit has a wrong name based on workaround definition and HSD. Wa_14014971508 allows the screen to continue to be updated when coming back from DC5/DC6 and SF_SINGLE_FULL_FRAME bit is not kept set in PSR2_MAN_TRK_CTL. Wa_16012604467 fixes underruns when exiting PSR2 when it is in one of its internal states. Wa_14014971508 is still in pending status in BSpec but by the time this is reviewed and ready to be merged it will be finalized. v2: - renamed register to ADLP_1_BASED_X_GRANULARITY - added comment about all ADL-P supported panels being 1 based X granularity BSpec: 54369 BSpec: 50054 Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210914212507.177511-5-jose.souza@intel.com
2021-09-17drm/i915/display/psr: Use drm damage helpers to calculate plane damaged areaJosé Roberto de Souza1-24/+13
drm_atomic_helper_damage_iter_init() + drm_atomic_for_each_plane_damage() returns the full plane area in case no damaged area was set by userspace or it was discarted by driver. This is important to fix the rendering of userspace applications that does frontbuffer rendering and notify driver about dirty areas but do not set any dirty clips. With this we don't need to worry about to check and mark the whole area as damaged in page flips. Another important change here is the move of drm_atomic_add_affected_planes() call, it needs to called late otherwise the area of all the planes would be added to pipe_clip and not saving power. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210914212507.177511-4-jose.souza@intel.com
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