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2022-06-13octeontx2-vf: Add support for adaptive interrupt coalescingSuman Ghosh1-1/+2
Fixes: 6e144b47f560 (octeontx2-pf: Add support for adaptive interrupt coalescing) Added support for VF interfaces as well. Signed-off-by: Suman Ghosh <sumang@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: smsc95xx: add support for Microchip EVB-LAN8670-USBParthiban Veerasooran1-0/+5
This patch adds support for Microchip's EVB-LAN8670-USB 10BASE-T1S ethernet device to the existing smsc95xx driver by adding the new USB VID/PID pairs. Signed-off-by: Parthiban Veerasooran <Parthiban.Veerasooran@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13nfp: support 48-bit DMA addressing for NFP3800Yinjun Zhang10-33/+52
48-bit DMA addressing is supported in NFP3800 HW and implemented in NFDK firmware, so enable this feature in driver now. Note that with this change, NFD3 firmware, which doesn't implement 48-bit DMA, cannot be used for NFP3800 any more. RX free list descriptor, used by both NFD3 and NFDK, is also modified to support 48-bit DMA. That's OK because the top bits is always get set to 0 when assigned with 40-bit address. Based on initial work of Jakub Kicinski <jakub.kicinski@netronome.com>. Signed-off-by: Yinjun Zhang <yinjun.zhang@corigine.com> Signed-off-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13spi: tegra210-quad: Multi-cs supportKrishna Yarlagadda1-2/+31
Tegra Grace and later chips can support upto 4 chip select lines for QUAD SPI. Added new compatible for Tegra Grace. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Link: https://lore.kernel.org/r/20220607114659.54314-2-kyarlagadda@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-13regulator: rpi-panel-attiny: Use backlight helperStephen Kitt1-5/+1
backlight_properties.fb_blank is deprecated. The states it represents are handled by other properties; but instead of accessing those properties directly, drivers should use the helpers provided by backlight.h. Instead of retrieving the backlight brightness in struct backlight_properties manually, and then checking whether the backlight should be on at all, use backlight_get_brightness() which does all this and insulates this from future changes. Signed-off-by: Stephen Kitt <steve@sk2.org> Cc: Liam Girdwood <lgirdwood@gmail.com> Cc: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220607185304.1128962-1-steve@sk2.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-13xilinx: Fix build on x86.David S. Miller1-4/+4
CONFIG_64BIT is not sufficient for checking for availability of iowrite64() and friends. Also, the out_addr helpers need to be inline. Fixes: b690f8df6497 ("net: axienet: Use iowrite64 to write all 64b descriptor pointers") Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: axienet: Use iowrite64 to write all 64b descriptor pointersAndy Chiu1-3/+18
According to commit f735c40ed93c ("net: axienet: Autodetect 64-bit DMA capability") and AXI-DMA spec (pg021), on 64-bit capable dma, only writing MSB part of tail descriptor pointer causes DMA engine to start fetching descriptors. However, we found that it is true only if dma is in idle state. In other words, dma would use a tailp even if it only has LSB updated, when the dma is running. The non-atomicity of this behavior could be problematic if enough delay were introduced in between the 2 writes. For example, if an interrupt comes right after the LSB write and the cpu spends long enough time in the handler for the dma to get back into idle state by completing descriptors, then the seconcd write to MSB would treat dma to start fetching descriptors again. Since the descriptor next to the one pointed by current tail pointer is not filled by the kernel yet, fetching a null descriptor here causes a dma internal error and halt the dma engine down. We suggest that the dma engine should start process a 64-bit MMIO write to the descriptor pointer only if ONE 32-bit part of it is written on all states. Or we should restrict the use of 64-bit addressable dma on 32-bit platforms, since those devices have no instruction to guarantee the write to LSB and MSB part of tail pointer occurs atomically to the dma. initial condition: curp = x-3; tailp = x-2; LSB = x; MSB = 0; cpu: |dma: iowrite32(LSB, tailp) | completes #(x-3) desc, curp = x-3 ... | tailp updated => irq | completes #(x-2) desc, curp = x-2 ... | completes #(x-1) desc, curp = x-1 ... | ... ... | completes #x desc, curp = tailp = x <= irqreturn | reaches tailp == curp = x, idle iowrite32(MSB, tailp + 4) | ... | tailp updated, starts fetching... | fetches #(x + 1) desc, sees cntrl = 0 | post Tx error, halt Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reported-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: axienet: make the 64b addresable DMA depends on 64b archecturesAndy Chiu2-24/+40
Currently it is not safe to config the IP as 64-bit addressable on 32-bit archectures, which cannot perform a double-word store on its descriptor pointers. The pointer is 64-bit wide if the IP is configured as 64-bit, and the device would process the partially updated pointer on some states if the pointer was updated via two store-words. To prevent such condition, we force a probe fail if we discover that the IP has 64-bit capability but it is not running on a 64-Bit kernel. This is a series of patch (1/2). The next patch must be applied in order to make 64b DMA safe on 64b archectures. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reported-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: ipa: derive channel from transactionAlex Elder3-29/+13
In gsi_channel_tx_queued(), we report when a transaction gets passed to hardware. Change that function so it takes transaction rather than a channel as its argument, and derive the channel from the transaction. Rename the function accordingly. Delete the header comments above the function definition; the ones above the declaration in "gsi_private.h" should suffice. In addition, the comments above gsi_channel_tx_update() do a fine job of explaining what's going on. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: ipa: determine channel from eventAlex Elder1-5/+21
Each event in an event ring describes the TRE whose completion caused the event. Currently, every event ring is dedicated to a single channel, so the channel is easily derived from the event ring. An event ring can actually be shared by more than one channel though, and to distinguish events for one channel from another, the event structure contains a field indicating which channel the event is associated with. In gsi_event_trans(), use the channel ID in an event to determine which channel the event is for. This makes the channel pointer now passed to that function irrelevant; pass the GSI pointer to that function instead. And although it shouldn't happen, warn if an event arrives that records a channel ID that's not in use, or if the event does not have a transaction associated with it. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: ipa: simplify endpoint transaction completionAlex Elder1-18/+5
When a GSI transaction completes, ipa_endpoint_trans_complete() is eventually called. That handles TX and RX completions separately, but ipa_endpoint_tx_complete() is a no-op. Instead, have ipa_endpoint_trans_complete() return immediately for a TX transaction, and incorporate code from ipa_endpoint_rx_complete() to handle RX transactions. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: ipa: rename endpoint->trans_tre_maxAlex Elder2-4/+4
The trans_tre_max field of the IPA endpoint structure is only used to limit the number of fragments allowed for an SKB being prepared for transmission. Recognizing that, rename the field skb_frag_max, and reduce its value by 1. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: ipa: rename channel->tlv_countAlex Elder5-32/+11
Each GSI channel has a TLV FIFO of a certain size, specified in the configuration data for an AP channel. That size dictates the maximum number of TREs that are allowed in a single transaction. The only way that value is used after initialization is as a limit on the number of TREs in a transaction; calling it "tlv_count" isn't helpful, and in fact gsi_channel_trans_tre_max() exists to sort of abstract it. Instead, rename the channel->tlv_count field trans_tre_max, and get rid of the helper function. Update a couple of comments as well. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: ipa: verify command channel TLV countAlex Elder1-12/+27
In commit 8797972afff3d ("net: ipa: remove command info pool"), the maximum number of IPA commands that would be sent in a single transaction was defined. That number can't exceed the size of the TLV FIFO on the command channel, and we can check that at runtime. To add this check, pass a new flag to gsi_channel_data_valid() to indicate the channel being checked is being used for IPA commands. Knowing that we can also verify the channel direction is correct. Use a new local variable that refers to the command-specific portion of the data being checked. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: hns3: fix tm port shapping of fibre port is incorrect after driver initializationGuangbin Huang3-4/+10
Currently in driver initialization process, driver will set shapping parameters of tm port to default speed read from firmware. However, the speed of SFP module may not be default speed, so shapping parameters of tm port may be incorrect. To fix this problem, driver sets new shapping parameters for tm port after getting exact speed of SFP module in this case. Fixes: 88d10bd6f730 ("net: hns3: add support for multiple media type") Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: hns3: fix PF rss size initialization bugJie Wang1-1/+3
Currently hns3 driver misuses the VF rss size to initialize the PF rss size in hclge_tm_vport_tc_info_update. So this patch fix it by checking the vport id before initialization. Fixes: 7347255ea389 ("net: hns3: refactor PF rss get APIs with new common rss get APIs") Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: hns3: restore tm priority/qset to default settings when tc disabledGuangbin Huang2-31/+65
Currently, settings parameters of schedule mode, dwrr, shaper of tm priority or qset of one tc are only be set when tc is enabled, they are not restored to the default settings when tc is disabled. It confuses users when they cat tm_priority or tm_qset files of debugfs. So this patch fixes it. Fixes: 848440544b41 ("net: hns3: Add support of TX Scheduler & Shaper to HNS3 driver") Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: hns3: modify the ring param print infoJie Wang1-1/+1
Currently tx push is also a ring param. So the original ring param print info in hns3_is_ringparam_changed should be adjusted. Fixes: 07fdc163ac88 ("net: hns3: refactor hns3_set_ringparam()") Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: hns3: don't push link state to VF if unaliveJian Shen1-0/+6
It's unnecessary to push link state to unalive VF, and the VF will query link state from PF when it being start works. Fixes: 18b6e31f8bf4 ("net: hns3: PF add support for pushing link status to VFs") Signed-off-by: Jian Shen <shenjian15@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13net: hns3: set port base vlan tbl_sta to false before removing old vlanGuangbin Huang1-0/+1
When modify port base vlan, the port base vlan tbl_sta needs to set to false before removing old vlan, to indicate this operation is not finish. Fixes: c0f46de30c96 ("net: hns3: fix port base vlan add fail when concurrent with reset") Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-13drm/i915/uc: remove accidental static from a local variableJani Nikula1-1/+1
The arrays are static const, but the pointer shouldn't be static. Fixes: 3d832f370d16 ("drm/i915/uc: Allow platforms to have GuC but not HuC") Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220511094619.27889-1-jani.nikula@intel.com (cherry picked from commit 5821a0bbb4c39960975d29d6b58ae290088db0ed)
2022-06-13drm/i915: Individualize fences before adding to dma_resv objNirmoy Das2-21/+30
_i915_vma_move_to_active() can receive > 1 fences for multiple batch buffers submission. Because dma_resv_add_fence() can only accept one fence at a time, change _i915_vma_move_to_active() to be aware of multiple fences so that it can add individual fences to the dma resv object. v6: fix multi-line comment. v5: remove double fence reservation for batch VMAs. v4: Reserve fences for composite_fence on multi-batch contexts and also reserve fence slots to composite_fence for each VMAs. v3: dma_resv_reserve_fences is not cumulative so pass num_fences. v2: make sure to reserve enough fence slots before adding. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5614 Fixes: 544460c33821 ("drm/i915: Multi-BB execbuf") Cc: <stable@vger.kernel.org> # v5.16+ Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220525095955.15371-1-nirmoy.das@intel.com (cherry picked from commit 420a07b841d03f6a436d8c06571c69aa5c783897) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2022-06-13drm/i915/gt: Fix memory leaks in per-gt sysfsAshutosh Dixit5-22/+19
All kmalloc'd kobjects need a kobject_put() to free memory. For example in previous code, kobj_gt_release() never gets called. The requirement of kobject_put() now results in a slightly different code organization. v2: s/gtn/gt/ (Andi) Fixes: b770bcfae9ad ("drm/i915/gt: create per-tile sysfs interface") Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Acked-by: Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a6f6686517c85fba61a0c45097f5bb4fe7e257fb.1653484574.git.ashutosh.dixit@intel.com (cherry picked from commit 69d6bf5c3754ffc491896632438417d1cedc2c68) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2022-06-13drm/i915/reset: Fix error_state_read ptr + offset useAlan Previn1-3/+12
Fix our pointer offset usage in error_state_read when there is no i915_gpu_coredump but buf offset is non-zero. This fixes a kernel page fault can happen when multiple tests are running concurrently in a loop and one is producing engine resets and consuming the i915 error_state dump while the other is forcing full GT resets. (takes a while to trigger). The dmesg call trace: [ 5590.803000] BUG: unable to handle page fault for address: ffffffffa0b0e000 [ 5590.803009] #PF: supervisor read access in kernel mode [ 5590.803013] #PF: error_code(0x0000) - not-present page [ 5590.803016] PGD 5814067 P4D 5814067 PUD 5815063 PMD 109de4067 PTE 0 [ 5590.803022] Oops: 0000 [#1] PREEMPT SMP NOPTI [ 5590.803026] CPU: 5 PID: 13656 Comm: i915_hangman Tainted: G U 5.17.0-rc5-ups69-guc-err-capt-rev6+ #136 [ 5590.803033] Hardware name: Intel Corporation Alder Lake Client Platform/AlderLake-M LP4x RVP, BIOS ADLPFWI1.R00. 3031.A02.2201171222 01/17/2022 [ 5590.803039] RIP: 0010:memcpy_erms+0x6/0x10 [ 5590.803045] Code: fe ff ff cc eb 1e 0f 1f 00 48 89 f8 48 89 d1 48 c1 e9 03 83 e2 07 f3 48 a5 89 d1 f3 a4 c3 66 0f 1f 44 00 00 48 89 f8 48 89 d1 <f3> a4 c3 0f 1f 80 00 00 00 00 48 89 f8 48 83 fa 20 72 7e 40 38 fe [ 5590.803054] RSP: 0018:ffffc90003a8fdf0 EFLAGS: 00010282 [ 5590.803057] RAX: ffff888107ee9000 RBX: ffff888108cb1a00 RCX: 0000000000000f8f [ 5590.803061] RDX: 0000000000001000 RSI: ffffffffa0b0e000 RDI: ffff888107ee9071 [ 5590.803065] RBP: 0000000000000000 R08: 0000000000000001 R09: 0000000000000001 [ 5590.803069] R10: 0000000000000001 R11: 0000000000000002 R12: 0000000000000019 [ 5590.803073] R13: 0000000000174fff R14: 0000000000001000 R15: ffff888107ee9000 [ 5590.803077] FS: 00007f62a99bee80(0000) GS:ffff88849f880000(0000) knlGS:0000000000000000 [ 5590.803082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 5590.803085] CR2: ffffffffa0b0e000 CR3: 000000010a1a8004 CR4: 0000000000770ee0 [ 5590.803089] PKRU: 55555554 [ 5590.803091] Call Trace: [ 5590.803093] <TASK> [ 5590.803096] error_state_read+0xa1/0xd0 [i915] [ 5590.803175] kernfs_fop_read_iter+0xb2/0x1b0 [ 5590.803180] new_sync_read+0x116/0x1a0 [ 5590.803185] vfs_read+0x114/0x1b0 [ 5590.803189] ksys_read+0x63/0xe0 [ 5590.803193] do_syscall_64+0x38/0xc0 [ 5590.803197] entry_SYSCALL_64_after_hwframe+0x44/0xae [ 5590.803201] RIP: 0033:0x7f62aaea5912 [ 5590.803204] Code: c0 e9 b2 fe ff ff 50 48 8d 3d 5a b9 0c 00 e8 05 19 02 00 0f 1f 44 00 00 f3 0f 1e fa 64 8b 04 25 18 00 00 00 85 c0 75 10 0f 05 <48> 3d 00 f0 ff ff 77 56 c3 0f 1f 44 00 00 48 83 ec 28 48 89 54 24 [ 5590.803213] RSP: 002b:00007fff5b659ae8 EFLAGS: 00000246 ORIG_RAX: 0000000000000000 [ 5590.803218] RAX: ffffffffffffffda RBX: 0000000000100000 RCX: 00007f62aaea5912 [ 5590.803221] RDX: 000000000008b000 RSI: 00007f62a8c4000f RDI: 0000000000000006 [ 5590.803225] RBP: 00007f62a8bcb00f R08: 0000000000200010 R09: 0000000000101000 [ 5590.803229] R10: 0000000000000001 R11: 0000000000000246 R12: 0000000000000006 [ 5590.803233] R13: 0000000000075000 R14: 00007f62a8acb010 R15: 0000000000200000 [ 5590.803238] </TASK> [ 5590.803240] Modules linked in: i915 ttm drm_buddy drm_dp_helper drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops prime_numbers nfnetlink br_netfilter overlay mei_pxp mei_hdcp x86_pkg_temp_thermal coretemp kvm_intel snd_hda_codec_hdmi snd_hda_intel snd_intel_dspcfg snd_hda_codec snd_hwdep snd_hda_core snd_pcm mei_me mei fuse ip_tables x_tables crct10dif_pclmul e1000e crc32_pclmul ptp i2c_i801 ghash_clmulni_intel i2c_smbus pps_core [last unloa ded: ttm] [ 5590.803277] CR2: ffffffffa0b0e000 [ 5590.803280] ---[ end trace 0000000000000000 ]--- Fixes: 0e39037b3165 ("drm/i915: Cache the error string") Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220311004311.514198-2-alan.previn.teres.alexis@intel.com (cherry picked from commit 3304033a1e69cd81a2044b4422f0d7e593afb4e6) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2022-06-13clk: renesas: rza1: Remove struct rz_cpgGeert Uytterhoeven1-18/+15
The register block base pointer as stored in the reg member of the rz_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to rz_cpg_register_clock(). After this, the data member is the only remaining member of the rz_cpg structure, so the whole structure can be replaced by the data member. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/2380285576edaa4ad3dc5eca7e0ca418f068c6ef.1654694831.git.geert+renesas@glider.be
2022-06-13clk: renesas: r8a7779: Remove struct r8a7779_cpgGeert Uytterhoeven1-18/+9
All but the data member of the r8a7779_cpg structure are unused, so the whole structure can be replaced by the single member used. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/eb94c0f6c54a4f3a7e0e07f12781333a700c0a05.1654694831.git.geert+renesas@glider.be
2022-06-13clk: renesas: r8a7778: Remove struct r8a7778_cpgGeert Uytterhoeven1-22/+9
All but the data member of the r8a7778_cpg structure are unused, so the whole structure can be replaced by the single member used. Remove the mapping of the CPG registers, as no code uses the mapped registers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/4123c1c40a901195f00a825d434553d2052829aa.1654694831.git.geert+renesas@glider.be
2022-06-13clk: renesas: sh73a0: Remove sh73a0_cpg.regGeert Uytterhoeven1-13/+13
The register block base pointer as stored in the reg member of the sh73a0_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to sh73a0_cpg_register_clock(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/5423e43d0cf518691965412fb510097d23ac5955.1654694831.git.geert+renesas@glider.be
2022-06-13clk: renesas: r8a7740: Remove r8a7740_cpg.regGeert Uytterhoeven1-10/+10
The register block base pointer as stored in the reg member of the r8a7740_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to r8a7740_cpg_register_clock(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/7ec676bcc36ef1eda02c2db328c527fc5fd44e99.1654694831.git.geert+renesas@glider.be
2022-06-13clk: renesas: r8a73a4: Remove r8a73a4_cpg.regGeert Uytterhoeven1-11/+11
The register block base pointer as stored in the reg member of the r8a73a4_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to r8a73a4_cpg_register_clock(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f835f3dfcf3bf754065e5002663952cc6341caac.1654694831.git.geert+renesas@glider.be
2022-06-13clk: renesas: r8a779f0: Add SDHI0 clockWolfram Sang1-0/+1
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220603233437.21819-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-13soc: renesas: rcar-sysc: Optimize rcar_sysc_area struct sizesGeert Uytterhoeven2-4/+4
Reduce the sizes of the rcar_sysc_area and rcar_gen4_sysc_area structures: - parent is in the range [-1..32] or [-1..64], so s8 is sufficient, - flags needs just 3 bits (for now), so u8 is plenty. This reduces kernel size by: - 288 bytes for an R-Car Gen1+Gen2 kernel (arm32), - 1772 bytes for an R-Car Gen3+Gen4 kernel (arm64). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/cbbc8f464743d636895c048de61aa610d75392de.1654701156.git.geert+renesas@glider.be
2022-06-13soc: renesas: r8a779a0-sysc: Fix A2DP1 and A2CV[2357] PDR valuesGeert Uytterhoeven1-5/+5
The PDR values for the A2DP1 and A2CV[2357] power areas on R-Car V3U are incorrect (copied-and-pasted from A2DP0 and A2CV[0146]). Fix them. Reported-by: Renesas Vietnam via Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Fixes: 1b4298f000064cc2 ("soc: renesas: r8a779a0-sysc: Add r8a779a0 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87bc2e70ba4082970cf8c65871beae4be3503189.1654696188.git.geert+renesas@glider.be
2022-06-13drm/probe-helper: abstract .get_modes() connector helper callJani Nikula1-10/+19
Abstract the .get_modes() connector helper call, including the override/firmware EDID fallback, for clarity. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a4de51efc246e4f5bcbf7b84d66bb49aaf7fd974.1654674560.git.jani.nikula@intel.com
2022-06-13drm/edid: add new interfaces around struct drm_edidJani Nikula1-24/+221
Add new functions drm_edid_read(), drm_edid_read_ddc(), and drm_edid_read_custom() to replace drm_get_edid() and drm_do_get_edid() for reading the EDID. The transition is expected to happen over a fairly long time. Note that the new drm_edid_read*() functions do not do any of the connector updates anymore. The reading and parsing will be completely separated from each other. Add new functions drm_edid_alloc(), drm_edid_dup(), and drm_edid_free() for allocating and freeing drm_edid containers. Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/5a6532a94cad6a79424f6d1918dbe7b7d607ac03.1654674560.git.jani.nikula@intel.com
2022-06-13drm/edid: keep track of alloc size in drm_do_get_edid()Jani Nikula1-8/+19
We'll want to return the allocated buffer size in the future. Keep track of it. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/8e4261d8c2947ea99240ea929f09a04878235f4e.1654674560.git.jani.nikula@intel.com
2022-06-13drm/edid: add block count and data helper functions for drm_edidJani Nikula1-7/+35
Add drm_edid based block count and data access helper functions that take the EDID allocated size into account. At the moment, the allocated size should always match the EDID size indicated by the extension count, but this will change in the future. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1a68c8667a88e7c451b001ad8bd86c8badb57fb8.1654674560.git.jani.nikula@intel.com
2022-06-13drm/edid: abstract cea data block collection sizeJani Nikula1-3/+21
Add a function to get the cea data block collection size. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/5339ab3249400a3c41001967e7ff2611b58e0425.1654674560.git.jani.nikula@intel.com
2022-06-13drm/edid: fix CTA data block collection size for CTA version 3Jani Nikula1-2/+0
The CTA Data Block Collection is valid only for CTA extension version 3. In versions 1 and 2, it is a reserved block, which we ignore. The DTD start offset (byte 2, or d in CTA-861 spec), which determines the CTA Data Block Collection size, is specified slightly differently for different versions: Version 1: d = offset for the byte following the reserved data block. If no data is provided in the reserved data block, then d=4. If no DTDs are provided, then d=0 Version 2: d = offset for the byte following the reserved data block. If no data is provided in the reserved data block, then d=4. If d=0, then no detailed timing descriptors are provided, and no data is provided in the reserved data block. Version 3: d = offset for the byte following the data block collection. If no data is provided in the data block collection, then d=4. If d=0, then no detailed timing descriptors are provided, and no data is provided in the data block collection. Ever since commit 9e50b9d55e9c ("drm: edid: Add some bounds checking"), we've interpreted 0 to mean there are no DTDs but it's all Data Blocks. Per the spec, Data Blocks are only valid for version 3, where we should interpret 0 to mean there are no data blocks. Follow the spec (and hope the EDIDs follow it too). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2a4c94417f024cbafc5d4ca0a74e4617fc4325d1.1654674560.git.jani.nikula@intel.com
2022-06-13clk: renesas: r8a779f0: Add thermal clockWolfram Sang1-0/+1
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220525151130.24103-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-13drm/syncobj: add missing error return code in drm_syncobj_transfer_to_timeline()Yang Yingliang1-1/+3
If dma_fence_unwrap_merge() fails, it should return error code in drm_syncobj_transfer_to_timeline() Fixes: ec8d985ff26f ("drm: use dma_fence_unwrap_merge() in drm_syncobj") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220613063454.2609364-1-yangyingliang@huawei.com
2022-06-13ata: libata-core: fix sloppy typing in ata_id_n_sectors()Sergey Shtylyov1-4/+6
The code multiplying the # of cylinders/heads/sectors in ata_id_n_sectors() to get a disk capacity implicitly uses the *int* type for that calculation and casting the result to 'u64' before returning ensues a sign extension. Explicitly casting the 'u16' typed multipliers to 'u32' results in avoiding a sign extension instruction and so in a more compact code... Found by Linux Verification Center (linuxtesting.org) with the SVACE static analysis tool. Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-06-13ata: pata_hpt3x2n: pass base DPLL frequency to hpt3x2n_pci_clock()Sergey Shtylyov1-8/+11
Currently, the base DPLL frequency is hardcoded in hpt3x2n_pci_clock(). Align with the updated 'pata_hpt37x' driver, where this frequency is a parameter to hpt37x_pci_clock(). While at it, also do the following to align with the 'pata_hpt37x' driver: - fix the 'freq' local variable's type; - remove the 'iobase' local variable; - extend the comment to the inl() call; - move the 'total' local variable's declaration. Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-06-13ata: pata_hpt37x: merge hpt374_read_freq() to hpt37x_pci_clock()Sergey Shtylyov1-24/+10
With hpt374_read_freq() implemented as a separate function, there's some code duplication going on, not to mention that this function is named incorrectly: it returns the f_CNT register value saved by BIOS, not the PCI clock frequency. Folding hpt374_read_freq() into hpt37x_pci_clock() saves 20 bytes of object code with x86_64 gcc 10.3.1... Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-06-13ata: pata_hpt37x: factor out hpt37x_pci_clock()Sergey Shtylyov1-43/+51
Factor out the PCI clock frequency detection code into hpt37x_pci_clock(), so that this driver becomes more like 'pata_hpt3x2n'. Note that I decided to change the way HPT374 is identified to using the PCI device ID... Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-06-13ata: pata_hpt37x: move claculating PCI clock from hpt37x_clock_slot()Sergey Shtylyov1-17/+28
hpt37x_init_one() incorrectly calls an averaged f_CNT register value 'freq' and hpt37x_clock_slot() takes that value as the 'freq' parameter -- rename the former variable to 'fcnt' and move the actual code calculating the PCI clock from hpt37x_clock_slot() to hpt37x_init_one(), along with adding the frequency clamping code, in preparation for the factoring out the PCI clock detection, so that this driver would become more like the 'pata_hpt3x2n' driver... Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-06-13ata: libata: Fix syntax errors in commentsXiang wangx1-1/+1
Delete the redundant word 'in'. Signed-off-by: Xiang wangx <wangxiang@cdjrlc.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-06-12drm: vkms: Alloc the compose frame using vzallocIgor Torrente1-3/+3
Currently, the memory to the composition frame is being allocated using the kzmalloc. This comes with the limitation of maximum size of one page size(which in the x86_64 is 4Kb and 4MB for default and hugepage respectively). Somes test of igt (e.g. kms_plane@pixel-format) uses more than 4MB when testing some pixel formats like ARGB16161616 and the following error were showing up when running kms_plane@plane-panning-bottom-right*: [drm:vkms_composer_worker [vkms]] *ERROR* Cannot allocate memory for output frame. This problem is addessed by allocating the memory using kvzalloc that circunvents this limitation. V5: Improve the commit message and drop the debugging issues in VKMS TO-DO(Melissa Wen). Reviewed-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Igor Torrente <igormtorrente@gmail.com> Signed-off-by: Melissa Wen <melissa.srw@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220404204515.42144-2-igormtorrente@gmail.com
2022-06-12drm/vkms: check plane_composer->map[0] before using itTales Lelo da Aparecida1-1/+1
Fix a copypasta error. The caller of compose_plane() already checks primary_composer->map. In contrast, plane_composer->map is never verified here before handling. Fixes: 7938f4218168 ("dma-buf-map: Rename to iosys-map") Reviewed-by: André Almeida <andrealmeid@riseup.net> Signed-off-by: Tales Lelo da Aparecida <tales.aparecida@gmail.com> Signed-off-by: Melissa Wen <melissa.srw@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220415111300.61013-2-tales.aparecida@gmail.com
2022-06-12drm/v3d: Add support for bcm2711Peter Robinson2-2/+4
Add compatible string and Kconfig options and help for bcm2711. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Signed-off-by: Melissa Wen <melissa.srw@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220603092610.1909675-4-pbrobinson@gmail.com
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