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2022-02-15usb: host: ehci-platform: Update brcm, xgs-iproc-ehci workaroundChris Packham1-2/+1
The original workaround was added prior to commit e4788edc730a ("USB: EHCI: Add alias for Broadcom INSNREG"). Now that brcm_insnreg exists in struct ehci_regs we can use that instead of having a local definition. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Link: https://lore.kernel.org/r/20220215000813.1779032-1-chris.packham@alliedtelesis.co.nz Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-02-15usb: host: {e|o}hci-dbg: kill useless 'ret' variable initializersSergey Shtylyov2-4/+4
The 'ret' local variables are often initialized to 0 but this value is unused, thus we can kill those initializers... Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Link: https://lore.kernel.org/r/901b7478-45b6-d8b3-f5c6-555712485232@omp.ru Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-02-15Merge branch 'for-linus' into for-nextTakashi Iwai2-20/+7
2022-02-15spi: amd: Add support for new controller versionMark Brown1-16/+71
Merge series from André Almeida <andrealmeid@collabora.com>: This series do some cleanup and add support for new controller version, AMDI0062.
2022-02-15mtd: spi-nor / spi / MFD: Convert intel-spi to SPI MEMMark Brown10-394/+706
Merge series from Mika Westerberg <mika.westerberg@linux.intel.com>: Based on discussion on the patch I sent some time ago here: http://lists.infradead.org/pipermail/linux-mtd/2021-June/086867.html it turns out that the preferred way to deal with the SPI flash controller drivers is through SPI MEM which is part of Linux SPI subsystem. This series does that for the intel-spi driver. This also renames the driver to follow the convention used in the SPI subsystem. The first patch improves the write protection handling to be slightly more safer. The following two patches do the conversion itself. Note the Intel SPI flash controller only allows commands such as read, write and so on and it internally uses whatever addressing etc. it figured from the SFDP on the flash device. base-commit: e783362eb54cd99b2cac8b3a9aeac942e6f6ac07
2022-02-15drm/i915: Change bigjoiner state tracking to use the pipe bitmaskVille Syrjälä9-152/+219
Get rid of the inflexible bigjoiner_linked_crtc pointer thing and just track things as a bitmask of pipes instead. We can also nuke the bigjoiner_slave boolean as the role of the pipe can be determined from its position in the bitmask. It might be possible to nuke the bigjoiner boolean as well if we make encoder.compute_config() do the bitmask assignment directly for the master pipe. But for now I left that alone so that encoer.compute_config() will just flag the state as needing bigjoiner, and the intel_atomic_check_bigjoiner() is still responsible for determining the bitmask. But that may have to change as the encoder may be in the best position to determine how exactly we should populate the bitmask. Most places that just looked at the single bigjoiner_linked_crtc now iterate over the whole bitmask, eliminating the singular slave pipe assumption. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220203183823.22890-11-ville.syrjala@linux.intel.com Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
2022-02-15drm/i915: Return both master and slave pipes from enabled_bigjoiner_pipes()Ville Syrjälä1-11/+14
Return both the master and slave pipe bitmasks from enabled_bigjoiner_pipes(). We'll have use for both during readout soon. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220203183823.22890-10-ville.syrjala@linux.intel.com Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
2022-02-15drm/i915: Use for_each_intel_crtc_in_pipe_mask() moreVille Syrjälä1-8/+4
Convert a few hand roller for_each_intel_crtc_in_pipe_mask() to the real thing. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220203183823.22890-9-ville.syrjala@linux.intel.com Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
2022-02-15drm/i915: Convert for_each_intel_crtc_mask() to take a pipe mask insteadVille Syrjälä2-19/+19
Often using pipes is more convenient than crtc indices. Convert the current for_each_intel_crtc_mask() to take a pipe mask instead of a crtc index mask, and rename it to for_each_intel_crtc_in_pipe_mask() to make it clear what it does. The current users of for_each_intel_crtc_mask() don't really care which kind of mask we use, but for other uses a pipe mask if better. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220203183823.22890-8-ville.syrjala@linux.intel.com Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
2022-02-15drm/i915: Introduce intel_crtc_is_bigjoiner_{slave,master}()Ville Syrjälä6-26/+39
Introduce helpers to query whether the crtc is the slave/master for bigjoiner. This decouples most places from the exact state layout we use to track this relationship, allowing us to change and extend it more easily. Performed with cocci: @@ expression S, E; @@ ( S->bigjoiner_slave = E; | - S->bigjoiner_slave + intel_crtc_is_bigjoiner_slave(S) ) @@ expression S, E; @@ ( - E && S->bigjoiner && !intel_crtc_is_bigjoiner_slave(S) + E && intel_crtc_is_bigjoiner_master(S) | - S->bigjoiner && !intel_crtc_is_bigjoiner_slave(S) + intel_crtc_is_bigjoiner_master(S) ) @@ expression S; @@ - (intel_crtc_is_bigjoiner_master(S)) + intel_crtc_is_bigjoiner_master(S) @@ expression S, E1, E2, E3; @@ - intel_crtc_is_bigjoiner_slave(S) ? E1 : S->bigjoiner ? E2 : E3 + intel_crtc_is_bigjoiner_slave(S) ? E1 : intel_crtc_is_bigjoiner_master(S) ? E2 : E3 @@ typedef bool; @@ + bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) + { + return crtc_state->bigjoiner_slave; + } + intel_master_crtc(...) {...} @@ typedef bool; @@ + bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) + { + return crtc_state->bigjoiner && !crtc_state->bigjoiner_slave; + } + intel_master_crtc(...) {...} @@ typedef bool; identifier S; @@ - bool is_trans_port_sync_mode(const struct intel_crtc_state *S); + bool is_trans_port_sync_mode(const struct intel_crtc_state *state); + bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state); + bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state); Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220203183823.22890-7-ville.syrjala@linux.intel.com Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
2022-02-15Merge branch irq/print_chip into irq/irqchip-nextMarc Zyngier6-99/+137
* irq/print_chip: : . : Convert irqchip drivers that use the .name field as a topology : description to the .irq_print_chip callback, which allows the : name to be made dymanic. The irq_chip structures are then made : 'const' in order to prevent further abuse. : . irqchip/versatile-fpga: Switch to dynamic chip name output irqchip/ts4800: Switch to dynamic chip name output irqchip/mvebu-pic: Switch to dynamic chip name output irqchip/lpc32xx: Switch to dynamic chip name output irqchip/gic: Switch to dynamic chip name output genirq/debugfs: Use irq_print_chip() when provided by irqchip genirq: Allow irq_chip registration functions to take a const irq_chip irqdomain: Let irq_domain_set_{info,hwirq_and_chip} take a const irq_chip Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-02-15dmaengine: idxd: restore traffic class defaults after wq resetDave Jiang1-2/+7
When clearing the group configurations, the driver fails to restore the default setting for DSA 1.x based devices. Add defaults in idxd_groups_clear_state() for traffic class configuration. Fixes: ade8a86b512c ("dmaengine: idxd: Set defaults for GRPCFG traffic class") Reported-by: Binuraj Ravindran <binuraj.ravindran@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164304123369.824298.6952463420266592087.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-15irqchip/versatile-fpga: Switch to dynamic chip name outputMarc Zyngier2-21/+26
Move the name output to the relevant callback, which allows us some nice cleanups (mostly owing to the fact that the driver is now DT only. We also drop a random include directive from the ftintc010 driver. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-8-maz@kernel.org
2022-02-15irqchip/ts4800: Switch to dynamic chip name outputMarc Zyngier1-8/+17
Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-7-maz@kernel.org
2022-02-15irqchip/mvebu-pic: Switch to dynamic chip name outputMarc Zyngier1-10/+18
Instead of overriding the name field, track the corresponding device and use the relevant callback to output its name. This allows us to make the irq_chip structure const. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-6-maz@kernel.org
2022-02-15irqchip/lpc32xx: Switch to dynamic chip name outputMarc Zyngier1-12/+22
Instead of overriding the name field with the device name, use the relevant callback. This allows us to make the irq_chip structure const. Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-5-maz@kernel.org
2022-02-15irqchip/gic: Switch to dynamic chip name outputMarc Zyngier1-48/+54
The last dynamic aspect of the GIC's irq_chip structure is the name that is associated to it. Move the output of that name to the relevant callback, which allows us to do a bit of cleanup and mark the structures const. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-4-maz@kernel.org
2022-02-15dmaengine: altera-msgdma: Remove useless DMA-32 fallback configurationChristophe JAILLET1-3/+1
As stated in [1], dma_set_mask() with a 64-bit mask never fails if dev->dma_mask is non-NULL. So, if it fails, the 32 bits case will also fail for the same reason. Simplify code and remove some dead code accordingly. [1]: https://lore.kernel.org/linux-kernel/YL3vSPK5DXTNvgdx@infradead.org/#t Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Olivier Dautricourt <olivier.dautricourt@orolia.com> Link: https://lore.kernel.org/r/01058ada3a0dea207212182ca7525060a204f1e1.1642232423.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-15iommu/sva: Assign a PASID to mm on PASID allocation and free it on mm exitFenghua Yu6-78/+19
PASIDs are process-wide. It was attempted to use refcounted PASIDs to free them when the last thread drops the refcount. This turned out to be complex and error prone. Given the fact that the PASID space is 20 bits, which allows up to 1M processes to have a PASID associated concurrently, PASID resource exhaustion is not a realistic concern. Therefore, it was decided to simplify the approach and stick with lazy on demand PASID allocation, but drop the eager free approach and make an allocated PASID's lifetime bound to the lifetime of the process. Get rid of the refcounting mechanisms and replace/rename the interfaces to reflect this new approach. [ bp: Massage commit message. ] Suggested-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Joerg Roedel <jroedel@suse.de> Link: https://lore.kernel.org/r/20220207230254.3342514-6-fenghua.yu@intel.com
2022-02-15i2c: pasemi: Drop I2C classes from platform driver variantMartin Povišer2-1/+1
Drop I2C device-probing classes from platform variant of the PASemi controller as it is only used on platforms where I2C devices should be instantiated in devicetree. (The I2C_CLASS_DEPRECATED flag is not raised as up to this point no devices relied on the old behavior.) Fixes: d88ae2932df0 ("i2c: pasemi: Add Apple platform driver") Signed-off-by: Martin Povišer <povik+lin@cutebit.org> Reviewed-by: Sven Peter <sven@svenpeter.dev> Acked-by: Hector Martin <marcan@marcan.st> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-02-15i2c: qup: allow COMPILE_TESTWolfram Sang1-1/+1
Driver builds fine with COMPILE_TEST. Enable it for wider test coverage and easier maintenance. Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-02-15i2c: imx: allow COMPILE_TESTWolfram Sang1-1/+1
Driver builds fine with COMPILE_TEST. Enable it for wider test coverage and easier maintenance. Signed-off-by: Wolfram Sang <wsa@kernel.org> Acked-by: Oleksij Rempel <o.rempel@pengutronix.de>
2022-02-15i2c: cadence: allow COMPILE_TESTWolfram Sang1-1/+1
Driver builds fine with COMPILE_TEST. Enable it for wider test coverage and easier maintenance. Signed-off-by: Wolfram Sang <wsa@kernel.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15i2c: designware: remove unneeded semicolonYang Li1-2/+2
Eliminate the following coccicheck warnings: ./drivers/i2c/busses/i2c-designware-amdpsp.c:172:2-3: Unneeded semicolon ./drivers/i2c/busses/i2c-designware-amdpsp.c:245:2-3: Unneeded semicolon Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Jan Dabros <jsd@semihalf.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-02-15i2c: designware-pci: Switch to use i2c_new_ccgx_ucsi()Andy Shevchenko2-25/+6
Instead of open coded variant switch to use i2c_new_ccgx_ucsi(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-02-15i2c: nvidia-gpu: Convert to use dev_err_probe()Andy Shevchenko1-12/+6
It's fine to call dev_err_probe() in ->probe() when error code is known. Convert the driver to use dev_err_probe(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-02-15i2c: nvidia-gpu: Use temporary variable for struct deviceAndy Shevchenko1-14/+14
Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-02-15i2c: nvidia-gpu: Switch to use i2c_new_ccgx_ucsi()Andy Shevchenko2-20/+7
Instead of open coded variant switch to use i2c_new_ccgx_ucsi(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-02-15i2c: Introduce common module to instantiate CCGx UCSIAndy Shevchenko4-0/+51
Introduce a common module to provide an API to instantiate UCSI device for Cypress CCGx Type-C controller. Individual bus drivers need to select this one on demand. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-02-15i2c: i801: Add support for Intel Raptor Lake PCH-SJarkko Nikula2-0/+4
Add SMBus PCI ID on Intel Raptor Lake PCH-S. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-02-15i2c: don't expose function which is only used internallyWolfram Sang2-1/+9
i2c_setup_smbus_alert() is only needed within the I2C core, so no need to expose it to other modules. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-02-14net/mlx5e: Optimize the common case condition in mlx5e_select_queueMaxim Mikityanskiy1-3/+8
Check all booleans for special queues at once, when deciding whether to go to the fast path in mlx5e_select_queue. Pack them into bitfields to have some room for extensibility. Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Optimize modulo in mlx5e_select_queueMaxim Mikityanskiy2-3/+24
To improve the performance of the modulo operation (%), it's replaced by a subtracting the divisor in a loop. The modulo is used to fix up an out-of-bounds value that might be returned by netdev_pick_tx or to convert the queue number to the channel number when num_tcs > 1. Both situations are unlikely, because XPS is configured not to pick higher queues (qid >= num_channels) by default, so under normal circumstances the flow won't go inside the loop, and it will be faster than %. num_tcs == 8 adds at most 7 iterations to the loop. PTP adds at most 1 iteration to the loop. HTB would add at most 256 iterations (when num_channels == 1), so there is an additional boundary check in the HTB flow, which falls back to % if more than 7 iterations are expected. Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Optimize mlx5e_select_queueMaxim Mikityanskiy1-16/+42
This commit optimizes mlx5e_select_queue for HTB and PTP cases by short-cutting some checks, without sacrificing performance of the common non-HTB non-PTP flow. 1. The HTB flow uses the fact that num_tcs == 1 to drop these checks (it's not possible to attach both mqprio and htb as the root qdisc). It's also enough to calculate `txq_ix % num_channels` only once, instead of twice. 2. The PTP flow drops the check for HTB and the second calculation of `txq_ix % num_channels`. Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Use READ_ONCE/WRITE_ONCE for DCBX trust stateMaxim Mikityanskiy2-6/+8
trust_state can be written while mlx5e_select_queue() is reading it. To avoid inconsistencies, use READ_ONCE and WRITE_ONCE for access and updates, and touch the variable only once per operation. Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Move repeating code that gets TC prio into a functionMaxim Mikityanskiy1-21/+15
Both mlx5e_select_queue and mlx5e_select_ptpsq contain the same logic to get user priority of a packet, according to the current trust state settings. This commit moves this repeating code to its own function. Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Use select queue parameters to sync with control flowMaxim Mikityanskiy5-73/+32
Start using the select queue parameters introduced in the previous commit to have proper synchronization with changing the configuration (such as number of channels and queues). It ensures that the state that mlx5e_select_queue() sees is always consistent and stays the same while the function is running. Also it allows mlx5e_select_queue to stop using data structures that weren't synchronized properly: txq2sq, channel_tc2realtxq, port_ptp_tc2realtxq. The last two are removed completely, as they were used only in mlx5e_select_queue. Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Move mlx5e_select_queue to en/selq.cMaxim Mikityanskiy4-113/+117
This commit moves mlx5e_select_queue and all stuff related to ndo_select_queue to en/selq.c to put all stuff working with selq into a separate file. Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Introduce select queue parametersMaxim Mikityanskiy6-5/+165
ndo_select_queue can be called at any time, and there is no way to stop the kernel from calling it to synchronize with configuration changes (real_num_tx_queues, num_tc). This commit introduces an internal way in mlx5e to sync mlx5e_select_queue() with these changes. The configuration needed by this function is stored in a struct mlx5e_selq_params, which is modified and accessed in an atomic way using RCU methods. The whole ndo_select_queue is called under an RCU lock, providing the necessary guarantees. The parameters stored in the new struct mlx5e_selq_params should only be used from inside mlx5e_select_queue. It's the minimal set of parameters needed for mlx5e_select_queue to do its job efficiently, derived from parameters stored elsewhere. That means that when the configuration change, mlx5e_selq_params may need to be updated. In such cases, the mlx5e_selq_prepare/mlx5e_selq_apply API should be used. struct mlx5e_selq contains two slots for the params: active and standby. mlx5e_selq_prepare updates the standby slot, and mlx5e_selq_apply swaps the slots in a safe atomic way using the RCU API. It integrates well with the open/activate stages of the configuration change flow. Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Sync txq2sq updates with mlx5e_xmit for HTB queuesMaxim Mikityanskiy2-4/+33
This commit makes necessary changes to guarantee that txq2sq remains stable while mlx5e_xmit is running. Proper synchronization is added for HTB TX queues. All updates to txq2sq are performed while the corresponding queue is disabled (i.e. mlx5e_xmit doesn't run on that queue). smp_wmb after each change guarantees that mlx5e_xmit can see the updated value after the queue is enabled. Comments explaining this mechanism are added to mlx5e_xmit. When an HTB SQ can be deleted (after deleting an HTB node), synchronize with RCU to wait for mlx5e_select_queue to finish and stop selecting that queue, before we re-enable it to avoid TX timeout watchdog alarms. Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Use a barrier after updating txq2sqMaxim Mikityanskiy1-2/+9
mlx5e_build_txq_maps updates txq2sq while TX queues are stopped. Add a barrier to ensure that these changes are visible before the queues are started and mlx5e_xmit reads from txq2sq. This commit handles regular TX queues. Synchronization between HTB TX queues and mlx5e_xmit is handled in the following commit. Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Disable TX queues before registering the netdevMaxim Mikityanskiy1-0/+1
Normally, the queues are disabled when the channels are deactivated, and enabled when the channels are activated. However, on register, the channels are not active, but the queues are enabled by default. This change fixes it, preventing mlx5e_xmit from running when the channels are deactivated in the beginning. Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Cleanup of start/stop all queuesMaxim Mikityanskiy1-3/+10
mlx5e_activate_priv_channels() and mlx5e_deactivate_priv_channels() start and stop all netdev TX queues. This commit removes the unneeded call to netif_tx_stop_all_queues and adds explanatory comments why these operations are needed. netif_tx_disable() does the same thing that netif_tx_stop_all_queues(), but taking the TX lock, thus guaranteeing that ndo_start_xmit is not running after return. That means that the netif_tx_stop_all_queues() call is not really necessary. The comments are improved: the TX watchdog timeout explanation is moved to the start stage where it really belongs (it used to be in both places, but was lost during some old refactoring) and rephrased in more details; the explanation for stopping all TX queues is added. Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Use FW limitation for max MPW WQEBBsAya Levin8-26/+35
Calculate maximal count of MPW WQEBBs on SQ's creation and store it there. Remove MLX5E_TX_MPW_MAX_NUM_DS and MLX5E_TX_MPW_MAX_WQEBBS. Update mlx5e_tx_mpwqe_is_full() and mlx5e_xdp_mpqwe_is_full() . Signed-off-by: Aya Levin <ayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Read max WQEBBs on the SQ from firmwareAya Levin8-26/+53
Prior to this patch the maximal value for max WQEBBs (WQE Basic Blocks, where WQE is a Work Queue Element) on the TX side was assumed to be 16 (fixed value). All firmware versions till today comply to this. In order to be more flexible and resilient, read from FW the corresponding: max_wqe_sz_sq. This value describes the maximum WQE size given in bytes, thus max WQEBBs is given by the division in WQEBB's byte size. The driver uses the top between 16 and the division result. This ensures synchronization between driver and firmware and avoids unexpected behavior. Store this value on the different SQs (Send Queues) for easy access. Signed-off-by: Aya Levin <ayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-14net/mlx5e: Remove unused tstamp SQ fieldTariq Toukan3-3/+0
Remove tstamp pointer in mlx5e_txqsq as it's no longer used after commit 7c39afb394c7 ("net/mlx5: PTP code migration to driver core section"). Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Aya Levin <ayal@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-02-15dmaengine: stm32-dma: set dma_device max_sg_burstAmelie Delaunay1-0/+1
Some stm32-dma consumers [1] rather use dma_get_slave_caps() to get max_sg_burst of their DMA channel as dma_get_max_seg_size() is specific to the DMA controller. All stm32-dma channels have the same features so, don't need to implement device_caps ops. Let dma_get_slave_caps() relies on dma_device configuration. That's why this patch sets dma_device max_sg_burst to the maximum segment size, which is the maximum of data items that can be transferred without software intervention. [1] https://lore.kernel.org/lkml/20220110103739.118426-1-alain.volmat@foss.st.com/ "media: stm32: dcmi: create a dma scatterlist based on DMA max_sg_burst value" Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Tested-by: Alain Volmat <alain.volmat@foss.st.com> Link: https://lore.kernel.org/r/20220117091740.11064-1-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-15dmaengine: imx-sdma: fix cyclic buffer race conditionTomasz Moń1-1/+3
Assign buffer ownership to SDMA after invoking descriptor callback to make sure that SDMA does not write to the buffer before it is read by the CPU. Signed-off-by: Tomasz Moń <tomasz.mon@camlingroup.com> Link: https://lore.kernel.org/r/20220117091955.1038937-2-tomasz.mon@camlingroup.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-15dmaengine: imx-sdma: restart cyclic channel if neededTomasz Moń1-0/+14
Under heavy load resulting in high interrupt latencies, it is possible for imx UART requests to completely fill DMA buffer. When DMA channel is triggered and no SDMA owned buffer is available, SDMA stops. Thanks to the autoRTS feature, there is no data loss due to the SDMA stop if the UART is using hardware flow control. According to DMA Engine API Guide, DMA cyclic operation is performed until explicitly stopped. Restart the buffer after handling channel loop if the channel was stopped by SDMA. Signed-off-by: Tomasz Moń <tomasz.mon@camlingroup.com> Link: https://lore.kernel.org/r/20220117091955.1038937-1-tomasz.mon@camlingroup.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-15dmaengine: shdma: Fix runtime PM imbalance on errorYongzhi Liu1-1/+3
pm_runtime_get_() increments the runtime PM usage counter even when it returns an error code, thus a matching decrement is needed on the error handling path to keep the counter balanced. Signed-off-by: Yongzhi Liu <lyz_cs@pku.edu.cn> Link: https://lore.kernel.org/r/1642311296-87020-1-git-send-email-lyz_cs@pku.edu.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
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