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2021-09-24pinctrl: renesas: rzg2l: Fix missing port register 21hBiju Das1-1/+1
Remove the duplicate port register 22h and replace it with missing port register 21h. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210922074140.22178-1-biju.das.jz@bp.renesas.com Fixes: c4c4637eb57f2a25 ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-24qed: Don't ignore devlink allocation failuresLeon Romanovsky2-7/+7
devlink is a software interface that doesn't depend on any hardware capabilities. The failure in SW means memory issues, wrong parameters, programmer error e.t.c. Like any other such interface in the kernel, the returned status of devlink APIs should be checked and propagated further and not ignored. Fixes: 755f982bb1ff ("qed/qede: make devlink survive recovery") Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24ice: Delete always true check of PF pointerLeon Romanovsky1-3/+0
PF pointer is always valid when PCI core calls its .shutdown() and .remove() callbacks. There is no need to check it again. Fixes: 837f08fdecbe ("ice: Add basic driver framework for Intel(R) E800 Series") Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24bnxt_en: Properly remove port parameter supportLeon Romanovsky1-13/+0
This driver doesn't have any port parameters and registers devlink port parameters with empty table. Remove the useless calls to devlink_port_params_register and _unregister. Fixes: da203dfa89ce ("Revert "devlink: Add a generic wake_on_lan port parameter"") Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Reviewed-by: Edwin Peer <edwin.peer@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24bnxt_en: Check devlink allocation and registration statusLeon Romanovsky3-21/+10
devlink is a software interface that doesn't depend on any hardware capabilities. The failure in SW means memory issues, wrong parameters, programmer error e.t.c. Like any other such interface in the kernel, the returned status of devlink APIs should be checked and propagated further and not ignored. Fixes: 4ab0c6a8ffd7 ("bnxt_en: add support to enable VF-representors") Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Reviewed-by: Edwin Peer <edwin.peer@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24clk: renesas: rzg2l: Fix clk status functionBiju Das1-1/+1
As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value 0 means clock is not supplied and 1 means clock is supplied. This patch fixes the issue by removing the inverted logic. Fixing the above, triggered following 2 issues 1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK. Fixed this issue by adding these clocks as critical clocks. 2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK. So will provide a fix in the DMA driver to turn on DMA_PCLK. Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210922112405.26413-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-24clk: renesas: r9a07g044: Add GbEthernet clock/resetBiju Das1-0/+10
Add ETH{0,1} clock/reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210922155145.28156-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-24clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK criticalBiju Das1-0/+2
Add IA55_CLK and DMAC_ACLK as critical clocks. Previously it worked ok, because of a bug in clock status function and the following patch in this series fixes the original bug. Fixes: c3e67ad6f5a2 ("dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions") Fixes: eb829e549ba6 ("clk: renesas: r9a07g044: Add DMAC clocks/resets") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210922112405.26413-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-24clk: renesas: rzg2l: Add support to handle coupled clocksBiju Das2-1/+81
The AXI and CHI clocks use the same register bit for controlling clock output. Add a new clock type for coupled clocks, which sets the CPG_CLKON_ETH.CLK[01]_ON bit when at least one clock is enabled, and clears the bit only when both clocks are disabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210922155145.28156-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-24clk: renesas: r9a07g044: Add ethernet clock sourcesBiju Das2-1/+21
Ethernet reference clock can be sourced from PLL5_FOUT3 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. This patch also renames the PLL5_DIV2 core clock to PLL5_250 to match with the register description as mentioned in RZ/G2L HW manual (Rev.1.00). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210922155145.28156-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-24clk: renesas: rzg2l: Add support to handle MUX clocksBiju Das2-0/+35
Add support to handle mux clocks in order to select a clock source from multiple sources. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210922155145.28156-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-24clk: renesas: r8a779a0: Add TPU clockWolfram Sang1-0/+1
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210901091725.35610-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-24net: mlx4: Add support for XDP_REDIRECTJoshua Roys1-0/+13
Signed-off-by: Joshua Roys <roysjosh@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24net: iosm: Use hrtimer_forward_now()Thomas Gleixner1-2/+2
hrtimer_forward_now() is providing the same functionality. Preparation for making hrtimer_forward() timer core code only. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Loic Poulain <loic.poulain@linaro.org> Cc: netdev@vger.kernel.org Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Jakub Kicinski <kuba@kernel.org> Cc: M Chetan Kumar <m.chetan.kumar@intel.com> Cc: Johannes Berg <johannes@sipsolutions.net> Cc: "David S. Miller" <davem@davemloft.net> Cc: Intel Corporation <linuxwwan@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24net: dsa: felix: accept "ethernet-ports" OF node nameVladimir Oltean1-1/+3
Since both forms are accepted, let's search for both when we pre-validate the PHY modes. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24net: enetc: fix the incorrect clearing of IF_MODE bitsVladimir Oltean1-2/+1
The enetc phylink .mac_config handler intends to clear the IFMODE field (bits 1:0) of the PM0_IF_MODE register, but incorrectly clears all the other fields instead. For normal operation, the bug was inconsequential, due to the fact that we write the PM0_IF_MODE register in two stages, first in phylink .mac_config (which incorrectly cleared out a bunch of stuff), then we update the speed and duplex to the correct values in phylink .mac_link_up. Judging by the code (not tested), it looks like maybe loopback mode was broken, since this is one of the settings in PM0_IF_MODE which is incorrectly cleared. Fixes: c76a97218dcb ("net: enetc: force the RGMII speed and duplex instead of operating in inband mode") Reported-by: Pavel Machek (CIP) <pavel@denx.de> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24drm/i915/fbc: Allow higher compression limits on FBC1Ville Syrjälä1-13/+7
On FBC1 we can specify an arbitrary cfb stride. The hw will simply throw away any compressed line that would exceed the specified limit and keep using the uncompressed data instead. Thus we can allow arbitrary compression limits. The one thing we have to keep in mind though is that the cfb stride is specified in units of 32B (gen2) or 64B (gen3+). Fortunately X-tile is already 128B (gen2) or 512B (gen3+) wide so as long as we limit outselves to the same 4x compression limit that FBC2 has we are guaranteed to have a sufficiently aligned cfb stride. Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210921152517.803-5-ville.syrjala@linux.intel.com
2021-09-24drm/i915/fbc: Implement Wa_16011863758 for icl+Ville Syrjälä1-2/+10
There's some kind of weird corner cases in FBC which requires FBC segments to be separated by at least one extra cacheline. Make sure that is present. v2: Respin to fit in with skl_fbc_min_cfb_stride() v3: Make it build Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210921181245.15091-1-ville.syrjala@linux.intel.com
2021-09-24drm/i915/fbc: Align FBC segments to 512B on glk+Ville Syrjälä2-3/+15
Apply the same 512 byte FBC segment alignment to glk+ as we use on skl+. The only real difference is that we now have a dedicated register for the FBC override stride. Not 100% sure which platforms really need the 512B alignment, but it's easiest to just do it on everything. Also the hardware no longer seems to misclaculate the CFB stride for linear, so we can omit the use of the override stride for linear unless the stride is misaligned. Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210921152517.803-3-ville.syrjala@linux.intel.com
2021-09-24drm/i915/fbc: Rework cfb stride/size calculationsVille Syrjälä2-61/+123
The code to calculate the cfb stride/size is a bit of mess. The cfb size is getting calculated based purely on the plane stride and plane height. That doesn't account for extra alignment we want for the cfb stride. The gen9 override stride OTOH is just calculated based on the plane width, and it does try to make things more aligned but any extra alignment added there is not considered in the cfb size calculations. So not at all convinced this is working as intended. Additionally the compression limit handling is split between the cfb allocation code and g4x_dpfc_ctl_limit() (for the 16bpp case), which is just confusing. Let's streamline the whole thing: - Start with the plane stride, convert that into cfb stride (cfb is always 4 bytes per pixel). All the calculations will assume 1:1 compression limit since that will give us the max values, and we don't yet know how much stolen memory we will be able to allocate - Align the cfb stride to 512 bytes on modern platforms. This guarantees the 4 line segment will be 512 byte aligned regardles of the final compression limit we choose later. The 512 byte alignment for the segment is required by at least some of the platforms, and just doing it always seems like the easiest option - Figure out if we need to use the override stride or not. For X-tiled it's never needed since the plane stride is already 512 byte aligned, for Y-tiled it will be needed if the plane stride is not a multiple of 512 bytes, and for linear it's apparently always needed because the hardware miscalculates the cfb stride as PLANE_STRIDE*512 instead of the PLANE_STRIDE*64 that it use with linear. - The cfb size will be calculated based on the aligned cfb stride to guarantee we actually reserved enough stolen memory and the FBC hw won't end up scribbling over whatever else is allocated in stolen - The compression limit handling we just do fully in the cfb allocation code to make things less confusing v2: Write the min cfb segment stride calculation in a more explicit way to make it clear what is going on v3: Remeber to update fbc->limit when changing to 16bpp Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v2 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210923042151.19052-1-ville.syrjala@linux.intel.com
2021-09-24Merge tag 'irqchip-fixes-5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgentThomas Gleixner6-13/+64
Pull irqchip fixes from Marc Zyngier: - Work around a bad GIC integration on a Renesas platform, where the interconnect cannot deal with byte-sized MMIO accesses - Cleanup another Renesas driver abusing the comma operator - Fix a potential GICv4 memory leak on an error path - Make the type of 'size' consistent with the rest of the code in __irq_domain_add() - Fix a regression in the Armada 370-XP IPI path - Fix the build for the obviously unloved goldfish-pic - Some documentation fixes Link: https://lore.kernel.org/r/20210924090933.2766857-1-maz@kernel.org
2021-09-24hwmon: (ltc2947) Properly handle errors when looking for the external clockUwe Kleine-König1-2/+6
The return value of devm_clk_get should in general be propagated to upper layer. In this case the clk is optional, use the appropriate wrapper instead of interpreting all errors as "The optional clk is not available". Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20210923201113.398932-1-u.kleine-koenig@pengutronix.de Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-09-24hwmon: (tmp421) fix rounding for negative valuesPaul Fertser1-16/+8
Old code produces -24999 for 0b1110011100000000 input in standard format due to always rounding up rather than "away from zero". Use the common macro for division, unify and simplify the conversion code along the way. Fixes: 9410700b881f ("hwmon: Add driver for Texas Instruments TMP421/422/423 sensor chips") Signed-off-by: Paul Fertser <fercerpav@gmail.com> Link: https://lore.kernel.org/r/20210924093011.26083-3-fercerpav@gmail.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-09-24hwmon: (tmp421) report /PVLD condition as faultPaul Fertser1-6/+3
For both local and remote sensors all the supported ICs can report an "undervoltage lockout" condition which means the conversion wasn't properly performed due to insufficient power supply voltage and so the measurement results can't be trusted. Fixes: 9410700b881f ("hwmon: Add driver for Texas Instruments TMP421/422/423 sensor chips") Signed-off-by: Paul Fertser <fercerpav@gmail.com> Link: https://lore.kernel.org/r/20210924093011.26083-2-fercerpav@gmail.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-09-24hwmon: (tmp421) handle I2C errorsPaul Fertser1-10/+28
Function i2c_smbus_read_byte_data() can return a negative error number instead of the data read if I2C transaction failed for whatever reason. Lack of error checking can lead to serious issues on production hardware, e.g. errors treated as temperatures produce spurious critical temperature-crossed-threshold errors in BMC logs for OCP server hardware. The patch was tested with Mellanox OCP Mezzanine card emulating TMP421 protocol for temperature sensing which sometimes leads to I2C protocol error during early boot up stage. Fixes: 9410700b881f ("hwmon: Add driver for Texas Instruments TMP421/422/423 sensor chips") Cc: stable@vger.kernel.org Signed-off-by: Paul Fertser <fercerpav@gmail.com> Link: https://lore.kernel.org/r/20210924093011.26083-1-fercerpav@gmail.com [groeck: dropped unnecessary line breaks] Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-09-24RDMA/hns: Work around broken constant propagation in gcc 8Jason Gunthorpe1-5/+6
gcc 8.3 and 5.4 throw this: In function 'modify_qp_init_to_rtr', ././include/linux/compiler_types.h:322:38: error: call to '__compiletime_assert_1859' declared with attribute error: FIELD_PREP: value too large for the field _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) [..] drivers/infiniband/hw/hns/hns_roce_common.h:91:52: note: in expansion of macro 'FIELD_PREP' *((__le32 *)ptr + (field_h) / 32) |= cpu_to_le32(FIELD_PREP( \ ^~~~~~~~~~ drivers/infiniband/hw/hns/hns_roce_common.h:95:39: note: in expansion of macro '_hr_reg_write' #define hr_reg_write(ptr, field, val) _hr_reg_write(ptr, field, val) ^~~~~~~~~~~~~ drivers/infiniband/hw/hns/hns_roce_hw_v2.c:4412:2: note: in expansion of macro 'hr_reg_write' hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); Because gcc has miscalculated the constantness of lp_pktn_ini: mtu = ib_mtu_enum_to_int(ib_mtu); if (WARN_ON(mtu < 0)) [..] lp_pktn_ini = ilog2(MAX_LP_MSG_LEN / mtu); Since mtu is limited to {256,512,1024,2048,4096} lp_pktn_ini is between 4 and 8 which is compatible with the 4 bit field in the FIELD_PREP. Work around this broken compiler by adding a 'can never be true' constraint on lp_pktn_ini's value which clears out the problem. Fixes: f0cb411aad23 ("RDMA/hns: Use new interface to modify QP context") Link: https://lore.kernel.org/r/0-v1-c773ecb137bc+11f-hns_gcc8_jgg@nvidia.com Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-09-24ath11k: monitor mode clean up to use separate APIsSeevalamuthu Mariappan4-51/+110
If monitor interface is enabled in co-exist mode, only local traffic are captured. It's caused by missing monitor vdev in co-exist mode. So, monitor mode clean up is done with separate Monitor APIs. For this, introduce flags monitor_started and monitor_vdev_created. Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-01725-QCAHKSWPL_SILICONZ-1 Co-developed-by: Miles Hu <milehu@codeaurora.org> Signed-off-by: Miles Hu <milehu@codeaurora.org> Co-developed-by: Vasanthakumar Thiagarajan <vthiagar@codeaurora.org> Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@codeaurora.org> Signed-off-by: Seevalamuthu Mariappan <seevalam@codeaurora.org> Signed-off-by: Jouni Malinen <jouni@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210721162053.46290-4-jouni@codeaurora.org
2021-09-24ath11k: add separate APIs for monitor modeSeevalamuthu Mariappan2-6/+370
Add separate APIs for monitor_vdev_create/monitor_vdev_delete and monitor_vdev_start/monitor_vdev_stop. Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-01725-QCAHKSWPL_SILICONZ-1 Co-developed-by: Miles Hu <milehu@codeaurora.org> Signed-off-by: Miles Hu <milehu@codeaurora.org> Co-developed-by: Vasanthakumar Thiagarajan <vthiagar@codeaurora.org> Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@codeaurora.org> Signed-off-by: Seevalamuthu Mariappan <seevalam@codeaurora.org> Signed-off-by: Jouni Malinen <jouni@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210721162053.46290-3-jouni@codeaurora.org
2021-09-24ath11k: move static function ath11k_mac_vdev_setup_sync to topSeevalamuthu Mariappan1-14/+14
This is to prepare for monitor mode clean up. No functional changes are done. Co-developed-by: Miles Hu <milehu@codeaurora.org> Signed-off-by: Miles Hu <milehu@codeaurora.org> Co-developed-by: Vasanthakumar Thiagarajan <vthiagar@codeaurora.org> Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@codeaurora.org> Signed-off-by: Seevalamuthu Mariappan <seevalam@codeaurora.org> Signed-off-by: Jouni Malinen <jouni@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210721162053.46290-2-jouni@codeaurora.org
2021-09-24rtw88: 8821c: correct 2.4G tx power for type 2/4 NICGuo-Feng Fan1-0/+3
NIC card saves calibrated TX power index in the efuse(ROM). Driver loads TX power idex when interface is up. The problem is type2/4 NICs loads 2.4G TX power index from wrong position. This patch corrects the offsets. So, driver loads real 2.4G TX power index for type 2/4 NICs. 2.4G performance increased when using correct TX power index. Signed-off-by: Guo-Feng Fan <vincent_fann@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210922023637.9357-2-pkshih@realtek.com
2021-09-24rtw88: 8821c: support RFE type4 wifi NICGuo-Feng Fan1-1/+12
RFE type4 is a new NIC which has one RF antenna shares with BT. RFE type4 HW is the same as RFE type2 but attaching antenna to aux antenna connector. RFE type2 attach antenna to main antenna connector. Load the same parameter as RFE type2 when initializing NIC. Signed-off-by: Guo-Feng Fan <vincent_fann@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210922023637.9357-1-pkshih@realtek.com
2021-09-24brcmfmac: Replace zero-length array with flexible array memberLen Baker1-1/+1
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use "flexible array members"[1] for these cases. The older style of one-element or zero-length arrays should no longer be used[2]. Also, make use of the struct_size() helper in devm_kzalloc(). [1] https://en.wikipedia.org/wiki/Flexible_array_member [2] https://www.kernel.org/doc/html/v5.14/process/deprecated.html#zero-length-and-one-element-arrays Signed-off-by: Len Baker <len.baker@gmx.com> Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210904092217.2848-1-len.baker@gmx.com
2021-09-24memory: tegra: Make use of the helper function devm_add_action_or_reset()Cai Huoqing1-4/+2
Use devm_add_action_or_reset() instead of devm_add_action() to simplify the error handling. Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Link: https://lore.kernel.org/r/20210922130002.586-1-caihuoqing@baidu.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-24mac80211_hwsim: enable 6GHz channelsRamon Fontes1-15/+141
Advertise 6 GHz channels with HE (and without HT/VHT) capabilities. Signed-off-by: Ramon Fontes <ramonreisfontes@gmail.com> Link: https://lore.kernel.org/r/20210923182805.27122-1-ramonreisfontes@gmail.com Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2021-09-24ath5k: fix building with LEDS=mArnd Bergmann2-7/+7
Randconfig builds still show a failure for the ath5k driver, similar to the one that was fixed for ath9k earlier: WARNING: unmet direct dependencies detected for MAC80211_LEDS Depends on [n]: NET [=y] && WIRELESS [=y] && MAC80211 [=y] && (LEDS_CLASS [=m]=y || LEDS_CLASS [=m]=MAC80211 [=y]) Selected by [m]: - ATH5K [=m] && NETDEVICES [=y] && WLAN [=y] && WLAN_VENDOR_ATH [=y] && (PCI [=y] || ATH25) && MAC80211 [=y] net/mac80211/led.c: In function 'ieee80211_alloc_led_names': net/mac80211/led.c:34:22: error: 'struct led_trigger' has no member named 'name' 34 | local->rx_led.name = kasprintf(GFP_KERNEL, "%srx", | ^ Copying the same logic from my ath9k patch makes this one work as well, stubbing out the calls to the LED subsystem. Fixes: b64acb28da83 ("ath9k: fix build error with LEDS_CLASS=m") Fixes: 72cdab808714 ("ath9k: Do not select MAC80211_LEDS by default") Fixes: 3a078876caee ("ath5k: convert LED code to use mac80211 triggers") Link: https://lore.kernel.org/all/20210722105501.1000781-1-arnd@kernel.org/ Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210920122359.353810-1-arnd@kernel.org
2021-09-24Merge tag 'kvmarm-fixes-5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-masterPaolo Bonzini1-0/+2
KVM/arm64 fixes for 5.15, take #1 - Add missing FORCE target when building the EL2 object - Fix a PMU probe regression on some platforms
2021-09-24Bluetooth: hci_h5: directly return hci_uart_register_device() ret-valHans de Goede1-6/+1
Since the hci_uart_register_device() call is the last thing we do in h5_serdev_probe() we can simply directly return its return-value. Cc: Archie Pusaka <apusaka@google.com> Suggested-by: Archie Pusaka <apusaka@google.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
2021-09-24Bluetooth: hci_h5: Fix (runtime)suspend issues on RTL8723BS HCIsHans de Goede1-9/+11
The recently added H5_WAKEUP_DISABLE h5->flags flag gets checked in h5_btrtl_open(), but it gets set in h5_serdev_probe() *after* calling hci_uart_register_device() and thus after h5_btrtl_open() is called, set this flag earlier. Also on devices where suspend/resume involves fully re-probing the HCI, runtime-pm suspend should not be used, make the runtime-pm setup conditional on the H5_WAKEUP_DISABLE flag too. This fixes the HCI being removed and then re-added every 10 seconds because it was being reprobed as soon as it was runtime-suspended. Fixes: 66f077dde749 ("Bluetooth: hci_h5: add WAKEUP_DISABLE flag") Fixes: d9dd833cf6d2 ("Bluetooth: hci_h5: Add runtime suspend") Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Archie Pusaka <apusaka@chromium.org> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
2021-09-24PCI: hv: Fix sleep while in non-sleep context when removing child devices from the busLong Li1-3/+10
In hv_pci_bus_exit, the code is holding a spinlock while calling pci_destroy_slot(), which takes a mutex. This is not safe for spinlock. Fix this by moving the children to be deleted to a list on the stack, and removing them after spinlock is released. Fixes: 94d22763207a ("PCI: hv: Fix a race condition when removing the device") Cc: "K. Y. Srinivasan" <kys@microsoft.com> Cc: Haiyang Zhang <haiyangz@microsoft.com> Cc: Stephen Hemminger <sthemmin@microsoft.com> Cc: Wei Liu <wei.liu@kernel.org> Cc: Dexuan Cui <decui@microsoft.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Rob Herring <robh@kernel.org> Cc: "Krzysztof Wilczyński" <kw@linux.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Michael Kelley <mikelley@microsoft.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/linux-hyperv/20210823152130.GA21501@kili/ Signed-off-by: Long Li <longli@microsoft.com> Reviewed-by: Wei Liu <wei.liu@kernel.org> Link: https://lore.kernel.org/r/1630365207-20616-1-git-send-email-longli@linuxonhyperv.com Signed-off-by: Wei Liu <wei.liu@kernel.org>
2021-09-24mlxsw: Add support for IP-in-IP with IPv6 underlay for Spectrum-2 and aboveAmit Cohen3-10/+309
Currently, mlxsw driver supports IP-in-IP only with IPv4 underlay. Add support for IPv6 underlay for Spectrum-2 and above. Most of the configurations are same to IPv4, the main difference between IPv4 and IPv6 is related to saving IP addresses. IPv6 addresses are saved as part of KVD and the relevant registers hold pointer to them. Add API for that as part of ipip_ops, so then only Spectrum-2 and above will save IPv6 addresses in this way. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24mlxsw: spectrum_router: Increase parsing depth for IPv6 decapsulationAmit Cohen3-0/+43
The Spectrum ASIC has a configurable limit on how deep into the packet it parses. By default, the limit is 96 bytes. For IP-in-IP packets, with IPv6 outer and inner headers, the default parsing depth is not enough and without increasing it such packets cannot be properly decapsulated. Use the existing API to set parsing depth, call it once for each decapsulation entry when it is created/destroyed. There is no need to protect the code with new mutex because 'router->lock' is already taken in these code paths. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24mlxsw: Add IPV6_ADDRESS kvdl entry typeAmit Cohen2-0/+3
Add support for allocating and freeing KVD entries for IPv6 addresses. These addresses are programmed by the RIPS register and referenced by the RATR and RTDP registers for IPv6 underlay encapsulation and decapsulation, respectively. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24mlxsw: spectrum_ipip: Add mlxsw_sp_ipip_gre6_opsAmit Cohen2-0/+66
Add operations for IP-in-IP GRE6. For now the function can_offload() returns false and the other functions warn as they should never be called. A later patch will add dedicated operations for Spectrum-2 which will support IPv6 underlay, so use 'mlxsw_sp1_' prefix for the new operations. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24mlxsw: Create separate ipip_ops_arr for different ASICsAmit Cohen3-4/+23
Currently, there is support for IP-in-IP only with IPv4 underlay for all supported Spectrum ASICs. The next patches will add support for IPv6 underlay only for Spectrum-2 and above. Add infrastructure for splitting IP-in-IP support between different ASICs - create separate ipip_ops_arr and add ipips_init function to set the right ops. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24mlxsw: reg: Add support for ritr_loopback_ipip6_pack()Amit Cohen1-0/+17
The RITR register is used to configure the router interface table. For IP-in-IP, it stores the underlay source IP address for encapsulation and also the ingress RIF for the underlay lookup. Add support for IPv6 IP-in-IP configuration. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24mlxsw: reg: Add support for ratr_ipip6_entry_pack()Amit Cohen1-0/+6
The RATR register is used to configure the Router Adjacency (next-hop) Table. For IP-in-IP entry, underlay destination IPv4 is saved as part of this register and underlay destination IPv6 is saved by RIPS register and RATR saves pointer to it. Add function for setting IPv6 IP-in-IP configuration. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24mlxsw: reg: Add support for rtdp_ipip6_pack()Amit Cohen1-5/+26
The RTDP register is used for configuring the tunnel decapsulation properties of NVE and IP-in-IP. Linux tunnels verify packets before decapsulation based on the packet's source IP, which must match tunnel remote IP. RTDP is used to configure decapsulation so that it filters out packets that are not IPv6 or have the wrong source IP or wrong GRE key. For IP-in-IP entry, source IPv4 is saved as part of this register and source IPv6 is saved by RIPS register and RTDP saves pointer to it. Create common function for configuring both IPv4 and IPv6 and add dedicated functions for each protocol. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24mlxsw: reg: Add Router IP version Six RegisterAmit Cohen1-0/+32
The RIPS register is used to store IPv6 addresses for use by the NVE and IP-in-IP. For IPv6 underlay support, RATR register needs to hold a pointer to the remote IPv6 address for encapsulation and RTDP register needs to hold a pointer to the local IPv6 address for decapsulation check. Add the required register for saving IPv6 addresses. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24mlxsw: Take tunnel's type into account when searching underlay deviceAmit Cohen3-13/+21
The function __mlxsw_sp_ipip_netdev_ul_dev_get() returns the underlay device that corresponds to the overlay device that it gets. Currently, this function assumes that the tunnel is IPv4 GRE, because it is the only one that is supported by mlxsw driver. This assumption will no longer be correct when IPv6 GRE support is added, resulting in wrong underlay device being returned. Instead, check 'ol_dev->type' and return the underlay device accordingly. Move the function to spectrum_ipip.c because spectrum_router.c should not be aware to tunnel type. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-24mlxsw: spectrum_ipip: Create common function for mlxsw_sp_ipip_ol_netdev_change_gre()Amit Cohen3-37/+59
The function mlxsw_sp_ipip_ol_netdev_change_gre4() contains code that can be shared between IPv4 and IPv6. The only difference is the way that arguments are taken from tunnel parameters, which are different between IPv4 and IPv6. For that, add structure 'mlxsw_sp_ipip_parms' to hold all the required parameters for the function and save it as part of 'struct mlxsw_sp_ipip_entry' instead of the existing structure that is not shared between IPv4 and IPv6. Add new operation as part of 'mlxsw_sp_ipip_ops' to initialize the new structure. Then mlxsw_sp_ipip_ol_netdev_change_gre{4,6}() will prepare the new structure and both will call the same function. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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