aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
AgeCommit message (Collapse)AuthorFilesLines
2021-06-18mxser: renumber mxser_cardsJiri Slaby1-43/+37
After the ISA cards removal in the previous patch, the mxser_cards array has holes in it. So renumber the array while updating PCI device's driver_data. Signed-off-by: Jiri Slaby <jslaby@suse.cz> Link: https://lore.kernel.org/r/20210618061516.662-3-jslaby@suse.cz Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-18mxser: drop ISA supportJiri Slaby2-342/+8
While mxser PCI cards are still around and produced (Moxa provided me with two recently), ISA cards are obsolete for a long time. I haven't seen anyone using the cards and the ISA code paths are barely tested. Hence, remove ISA support from mxser driver so that we can clean the driver up. Signed-off-by: Jiri Slaby <jslaby@suse.cz> Link: https://lore.kernel.org/r/20210618061516.662-2-jslaby@suse.cz Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-18staging: rtl8723bs: rtw_efuse: Fix coding styleShreyas Krishnakumar1-7/+4
Remove unnecessary braces around single statement blocks as warned by checkpatch.pl Signed-off-by: Shreyas Krishnakumar <shreyaskumar1035@gmail.com> Link: https://lore.kernel.org/r/20210616073921.156814-1-shreyaskumar1035@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-18staging: rtl8723bs: hal: use eth_broadcast_addr() to assign broadcast addressYang Yingliang1-2/+1
Using eth_broadcast_addr() to assign broadcast address instead of copying from an array that contains the all-ones broadcast address. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20210616081243.2511663-4-yangyingliang@huawei.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-18staging: rtl8723bs: core: use eth_broadcast_addr() to assign broadcast addressYang Yingliang1-5/+3
Using eth_broadcast_addr() to assign broadcast address instead of copying from an array that contains the all-ones broadcast address. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20210616081243.2511663-3-yangyingliang@huawei.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-18staging: rtl8723bs: os_dep: use eth_broadcast_addr() to assign broadcast addressYang Yingliang2-4/+3
Using eth_broadcast_addr() to assign broadcast address instead of memset() or copying from an array that contains the all-ones broadcast address. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20210616081243.2511663-2-yangyingliang@huawei.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-18staging: r8188eu/core: remove the check for NULL pointer in _rtw_enqueue_cmd()Qiang Ma1-5/+0
Remove the check for _rtw_enqueue_cmd(), because rtw_enqueue_cmd() already has a check of NULL pointer, so this condition is not possible. Signed-off-by: Qiang Ma <maqianga@uniontech.com> Link: https://lore.kernel.org/r/20210616125332.31674-1-maqianga@uniontech.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-18staging: ks7010: Wrap macro definitions in parenthesisCaleb D.S. Brzezinski1-12/+12
Wrap the definition of TX_RATE_* constants in parenthesis to prevent incorrect casting during expansion, as recommended by checkpatch.pl. Signed-off-by: Caleb D.S. Brzezinski <calebdsb@protonmail.com> Link: https://lore.kernel.org/r/20210616212552.117604-1-calebdsb@protonmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-18staging: rts5208: remove redundant continue statementColin Ian King1-1/+0
The continue statement at the end of a for-loop has no effect, remove it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Addresses-Coverity: ("Continue has no effect") Link: https://lore.kernel.org/r/20210617120411.11612-1-colin.king@canonical.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-18staging: android: ashmem: add size field in procfs fdinfoliuhailong1-0/+2
add this information to help user to find ashmem problem. ashmem leak scenario: -000|fd = ashmem_create_region -001|mmap and pagefault -002|munmap -003|forget close(fd) <---- which lead to ashmem leak Signed-off-by: liuhailong <liuhailong@oppo.com> 收件人: 刘海龙(DuckBuBee) <liuhailong@oppo.com> Link: https://lore.kernel.org/r/20210618095035.32410-1-liuhailong@oppo.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-18sched: Change task_struct::statePeter Zijlstra1-3/+3
Change the type and name of task_struct::state. Drop the volatile and shrink it to an 'unsigned int'. Rename it in order to find all uses such that we can use READ_ONCE/WRITE_ONCE as appropriate. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Daniel Bristot de Oliveira <bristot@redhat.com> Acked-by: Will Deacon <will@kernel.org> Acked-by: Daniel Thompson <daniel.thompson@linaro.org> Link: https://lore.kernel.org/r/20210611082838.550736351@infradead.org
2021-06-18sched: Unbreak wakeupsPeter Zijlstra3-16/+8
Remove broken task->state references and let wake_up_process() DTRT. The anti-pattern in these patches breaks the ordering of ->state vs COND as described in the comment near set_current_state() and can lead to missed wakeups: (OoO load, observes RUNNING)<-. for (;;) { | t->state = UNINTERRUPTIBLE; | smp_mb(); ,-----> | (observes !COND) | / if (COND) ---------' | COND = 1; break; `- if (t->state != RUNNING) wake_up_process(t); // not done schedule(); // forever waiting } t->state = TASK_RUNNING; Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Davidlohr Bueso <dbueso@suse.de> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20210611082838.160855222@infradead.org
2021-06-18Merge branch 'sched/urgent' into sched/core, to resolve conflictsIngo Molnar268-1082/+2206
This commit in sched/urgent moved the cfs_rq_is_decayed() function: a7b359fc6a37: ("sched/fair: Correctly insert cfs_rq's to list on unthrottle") and this fresh commit in sched/core modified it in the old location: 9e077b52d86a: ("sched/pelt: Check that *_avg are null when *_sum are") Merge the two variants. Conflicts: kernel/sched/fair.c Signed-off-by: Ingo Molnar <mingo@kernel.org>
2021-06-18drivers: qcom: pinctrl: Add pinctrl driver for sm6125Martin Botka3-0/+1287
This patch adds pinctrl driver for sm6125. Signed-off-by: Martin Botka <martin.botka@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210614172713.558192-2-martin.botka@somainline.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-18pinctrl: microchip-sgpio: Put fwnode in error case during ->probe()Andy Shevchenko1-1/+3
device_for_each_child_node() bumps a reference counting of a returned variable. We have to balance it whenever we return to the caller. Fixes: 7e5ea974e61c ("pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO") Cc: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20210606191940.29312-1-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-18mtd: rawnand: omap: Add larger page NAND chips supportMiquel Raynal2-67/+114
There is no reason to be limited to 4kiB page NAND chips just because this is the maximum length the ELM is able to handle in one go. Just call the ELM several times and it will process as many data as needed. Here we introduce the concept of ECC page (which is at most 4kiB). The ELM will be sought as many times as there are ECC pages. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Ryan Barnett <ryan.barnett@collins.com> Link: https://lore.kernel.org/linux-mtd/20210610134906.3503303-6-miquel.raynal@bootlin.com
2021-06-18mtd: rawnand: omap: Various style fixesMiquel Raynal1-5/+7
Fix the comments style, declare the variables in a reverse Christmas tree order, add an upper case character at the beginning of a sentence. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210610134906.3503303-5-miquel.raynal@bootlin.com
2021-06-18mtd: rawnand: omap: Check return valuesMiquel Raynal1-9/+21
Check the return value of many helpers which might return error codes. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210610134906.3503303-4-miquel.raynal@bootlin.com
2021-06-18mtd: rawnand: omap: Rename a macroMiquel Raynal1-8/+8
The macro BADBLOCK_MARKER_LENGTH is pretty long and could be reduced to BBM_LEN which is more handy to use in the code. This is a purely cosmetic change and is only done to avoid further change to contain 100+ char lines just because of this definition. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210610134906.3503303-3-miquel.raynal@bootlin.com
2021-06-18mtd: rawnand: omap: Aggregate the HW configuration of the ELMMiquel Raynal1-19/+11
Instead of calling elm_config() for each possible BCH configuration, just save the BCH configuration that must be applied and use it in a single call at the bottom. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210610134906.3503303-2-miquel.raynal@bootlin.com
2021-06-18mtd: rawnand: pl353: Add support for the ARM PL353 SMC NAND controllerMiquel Raynal3-0/+1203
This hardware controller is embedded in XilinX Zynq-7000 SoCs and has partial support for Hamming ECC correction. This work is inspired from the original contributions of Punnaiah Choudary Kalluri and Naga Sureshkumar Relli. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Michael Walle <michael@walle.cc> [on zynq-7000] Link: https://lore.kernel.org/linux-mtd/20210610082040.2075611-19-miquel.raynal@bootlin.com
2021-06-18mtd: rawnand: qcom: avoid writing to obsolete registerMd Sadre Alam1-6/+12
QPIC_EBI2_ECC_BUF_CFG register got obsolete from QPIC V2.0 onwards. Avoid writing this register if QPIC version is V2.0 or newer. Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1623134916-562-1-git-send-email-mdalam@codeaurora.org
2021-06-18mtd: rawnand: marvell: Minor documentation correctionSouptick Joarder1-1/+1
Kernel test robot throws below warning -> drivers/mtd/nand/raw/marvell_nand.c:454: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst Minor documentation correction. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Souptick Joarder <jrdr.linux@gmail.com> Cc: Randy Dunlap <rdunlap@infradead.org> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210607193736.4654-1-jrdr.linux@gmail.com
2021-06-18mtd: rawnand: r852: use DEVICE_ATTR_RO() helper macroZhen Lei1-4/+3
Use DEVICE_ATTR_RO() helper macro instead of plain DEVICE_ATTR(), which makes the code a bit shorter and easier to read. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210603123339.12089-1-thunder.leizhen@huawei.com
2021-06-18mtd: spinand: add SPI-NAND MTD resume handlerPatrice Chotard1-0/+17
After power up, all SPI NAND's blocks are locked. Only read operations are allowed, write and erase operations are forbidden. The SPI NAND framework unlocks all the blocks during its initialization. During a standby low power, the memory is powered down, losing its configuration. During the resume, the QSPI driver state is restored but the SPI NAND framework does not reconfigured the memory. This patch adds SPI-NAND MTD PM handlers for resume ops. SPI NAND resume op re-initializes SPI NAND flash to its probed state. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210602094913.26472-4-patrice.chotard@foss.st.com
2021-06-18mtd: spinand: Add spinand_init_flash() helperPatrice Chotard1-29/+45
Add spinand_init_flash() helper which implement all needed init for future SPI-NAND resume ops. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210602094913.26472-3-patrice.chotard@foss.st.com
2021-06-18mtd: spinand: add spinand_read_cfg() helperPatrice Chotard1-9/+20
Put REG_CFG reading code in spinand_read_cfg(). This function will be needed by the future SPI-NAND resume ops. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210602094913.26472-2-patrice.chotard@foss.st.com
2021-06-18mtd: rawnand: marvell: add missing clk_disable_unprepare() on error in marvell_nfc_resume()Yang Yingliang1-1/+3
Add clk_disable_unprepare() on error path in marvell_nfc_resume(). Fixes: bd9c3f9b3c00 ("mtd: rawnand: marvell: add suspend and resume hooks") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210601125814.3260364-1-yangyingliang@huawei.com
2021-06-18mtd: rawnand: arasan: Finer grain NV-DDR configurationMiquel Raynal1-2/+54
Add support for the timings register which may improve a bit the overall throughput. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210527084959.208804-2-miquel.raynal@bootlin.com
2021-06-18mtd: rawnand: arasan: Rename the data interface registerMiquel Raynal1-7/+7
There are 2 timing registers: - "data interface" - "timings" So far, the "data interface" register was named "timings" which begins misleading when bringing support for the "timings" register. Rename it to "data_iface". Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210527084959.208804-1-miquel.raynal@bootlin.com
2021-06-18mtd: rawnand: onfi: Fix endianness when reading NV-DDR valuesMiquel Raynal1-3/+3
Without the use of le16_to_cpu(), these accesses would have been wrong on a big-endian machine. Reported-by: kernel test robot <lkp@intel.com> Fixes: 45606518f961 ("mtd: rawnand: Add onfi_fill_nvddr_interface_config() helper") Fixes: 9310668fb60a ("mtd: rawnand: Retrieve NV-DDR timing modes from the ONFI parameter page") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210527084913.208635-1-miquel.raynal@bootlin.com
2021-06-18mtd: rawnand: arasan: Use the right DMA maskMiquel Raynal1-0/+4
Xilinx ZynqMP SoC and the Arasan controller support 64-bit DMA addressing. Define the right mask otherwise the default is 32 and some accesses may overflow the default mask. Reported-by: Jorge Courett <jorge.courett@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Jorge Courett <jorge.courett@gmail.com> Link: https://lore.kernel.org/linux-mtd/20210527084548.208429-1-miquel.raynal@bootlin.com
2021-06-18Revert "USB: misc: Add onboard_usb_hub driver"Greg Kroah-Hartman3-515/+0
This reverts commit b4e326165e21d6a11483f6a4de2174b933413554 as the patch series is causing build issues in linux-next at the moment. Cc: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/YMuRcrE8xlWnFSWW@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-18Revert "usb: host: xhci-plat: Create platform device for onboard hubs in probe()"Greg Kroah-Hartman3-9/+0
This reverts commit c950686b382d0ea5234545fcce252c9e63d7b7a9 as the patch series is causing build issues in linux-next at the moment. Cc: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/YMuRcrE8xlWnFSWW@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-18opp: Allow required-opps to be used for non genpd use casesHsin-Yi Wang2-22/+12
Don't limit required_opp_table to genpd only. One possible use case is cpufreq based devfreq governor, which can use required-opps property to derive devfreq from cpufreq. Though the OPP core still doesn't support non-genpd required-opps in _set_required_opps(). Suggested-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> [ Viresh: Update _set_required_opps() to check for genpd ] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2021-06-18Merge tag 'amd-drm-next-5.14-2021-06-16' of https://gitlab.freedesktop.org/agd5f/linux into drm-nextDave Airlie102-888/+2345
amd-drm-next-5.14-2021-06-16: amdgpu: - Aldebaran fixes - Expose asic independent throttler status - BACO fixes for navi1x - Smartshift fixes - Misc code cleanups - RAS fixes for Sienna Cichlid - Gamma verificaton fixes - DC LTTPR fixes - DP AUX timeout handling fixes - GFX9, 10 powergating fixes amdkfd: - TLB flush fixes when using SDMA - Locking fixes - SVM fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210617031719.4013-1-alexander.deucher@amd.com
2021-06-17drm/i915: Add support for explicit L3BANK steeringMatt Roper3-60/+46
Because Render Power Gating restricts us to just a single subslice as a valid steering target for reads of multicast registers in a SUBSLICE range, the default steering we setup at init may not lead to a suitable target for L3BANK multicast register. In cases where it does not, use explicit runtime steering whenever an L3BANK multicast register is read. While we're at it, let's simplify the function a little bit and drop its support for gen10/CNL since no such platforms ever materialized for real use. Multicast register steering is already an area that causes enough confusion; no need to complicate it with what's effectively dead code. v2: - Use gt->uncore instead of gt->i915->uncore. (Tvrtko) - Use {} as table terminator. (Rodrigo) v3: - L3bank fuse register is a disable mask rather than an enable mask. We need to invert it before use. (CI) v4: - L3bank ID goes in the subslice field, not the slice field. (CI) Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210617211425.1943662-4-matthew.d.roper@intel.com
2021-06-17drm/i915: Add GT support for multiple types of multicast steeringMatt Roper5-13/+142
Although most of our multicast registers are replicated per-subslice, we also have a small number of multicast registers that are replicated per-l3 bank instead. For both types of multicast registers we need to make sure we steer reads of these registers to a valid instance. Ideally we'd like to find a specific instance ID that would steer reads of either type of multicast register to a valid instance (i.e., not fused off and not powered down), but sometimes the combination of part-specific fusing and the additional restrictions imposed by Render Power Gating make it impossible to find any overlap between the set of valid subslices and valid l3 banks. This problem will become even more noticeable on our upcoming platforms since they will be adding additional types of multicast registers with new types of replication and rules for finding valid instances for reads. To handle this we'll continue to pick a suitable subslice instance at driver startup and program this as the default (sliceid,subsliceid) setting in the steering control register (0xFDC). In cases where we need to read another type of multicast GT register, but the default subslice steering would not correspond to a valid instance, we'll explicitly re-steer the single read to a valid value, perform the read, and then reset the steering to it's "subslice" default. This patch adds the general functionality to prepare for this explicit steering of other multicast register types. We'll plug L3 bank steering into this in the next patch, and then add additional types of multicast registers when the support for our next upcoming platform arrives. v2: - Use entry->end==0 as table terminator. (Rodrigo) - Grab forcewake in wa_list_verify() now that we're using accessors that assume forcewake is already held. v3: - Fix loop condition when iterating over steering range tables. (Rodrigo) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210617211425.1943662-3-matthew.d.roper@intel.com
2021-06-17drm/i915: extract steered reg access to common functionDaniele Ceraolo Spurio3-39/+63
New steering cases will be added in the follow-up patches, so prepare a common helper to avoid code duplication. Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210617211425.1943662-2-matthew.d.roper@intel.com
2021-06-17EDAC/Intel: Do not load EDAC driver when running as a guestLuck, Tony4-0/+12
There's little to no point in loading an EDAC driver running in a guest: 1) The CPU model reported by CPUID may not represent actual h/w 2) The hypervisor likely does not pass in access to memory controller devices 3) Hypervisors generally do not pass corrected error details to guests Add a check in each of the Intel EDAC drivers for X86_FEATURE_HYPERVISOR and simply return -ENODEV in the init routine. Acked-by: Borislav Petkov <bp@suse.de> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20210615174419.GA1087688@agluck-desk2.amr.corp.intel.com
2021-06-17EDAC/igen6: Add Intel Alder Lake SoC supportQiuxu Zhuo1-11/+73
Alder Lake SoC shares the same memory controller and In-Band ECC (IBECC) IP with Tiger Lake SoC. Like Tiger Lake, it also has two memory controllers each associated one IBECC instance. The minor differences include the MMIO offset of each memory controller and the type of memory error address logged in the IBECC. So add Alder Lake compute die IDs, adjust the MMIO offset for each memory controller and handle the type of memory error address logged in the IBECC for Alder Lake EDAC support. Tested-by: Vrukesh V Panse <vrukesh.v.panse@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20210611170123.1057025-7-tony.luck@intel.com
2021-06-17EDAC/igen6: Add Intel Tiger Lake SoC supportQiuxu Zhuo1-20/+253
Tiger Lake SoC shares the same memory controller and In-Band ECC (IBECC) IP with Elkhart Lake SoC. The main differences are that Tiger Lake has two memory controllers each associated with one IBECC and uses Machine Check for the memory error notification. So add Tiger Lake compute die IDs, MCE decoding chain registration, and memory slice decoding for Tiger Lake EDAC support. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20210611170123.1057025-6-tony.luck@intel.com
2021-06-17EDAC/igen6: Add Intel ICL-NNPI SoC supportQiuxu Zhuo1-0/+29
The Ice Lake Neural Network Processor for Deep Learning Inference (ICL-NNPI) SoC shares the same memory controller and In-Band ECC with Elkhart Lake SoC. Add the ICL-NNPI compute die IDs for EDAC support. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20210611170123.1057025-5-tony.luck@intel.com
2021-06-17EDAC/i10nm: Add support for high bandwidth memoryQiuxu Zhuo3-19/+148
A future Xeon processor will include in-package HBM (high bandwidth memory). The in-package HBM memory controller shares the same architecture with the regular DDR memory controller. Add the HBM memory controller devices for EDAC support. Tested-by: Hongyu Ning <hongyu.ning@linux.intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20210611170123.1057025-4-tony.luck@intel.com
2021-06-17EDAC/i10nm: Add detection of memory levels for ICX/SPR serversQiuxu Zhuo2-0/+42
Current i10nm_edac driver is only for system configured in 1-level memory. If the system is configured in 2-level memory, the driver doesn't report the 1st level memory DIMM for the error address, even if the error occurs in the 1st level memory. Both Ice Lake servers and Sapphire Rapids servers can be configured in 2-level memory. Add detection of memory levels to i10nm_edac for the two kinds of servers so that the driver can report the 2nd level memory DIMM or the 1st level memory DIMM according to error source. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20210611170123.1057025-3-tony.luck@intel.com
2021-06-17EDAC/skx_common: Add new ADXL components for 2-level memoryQiuxu Zhuo2-11/+67
Some Intel servers may configure memory in 2 levels, using fast "near" memory (e.g. DDR) as a cache for larger, slower, "far" memory (e.g. 3D X-point). In these configurations the BIOS ADXL address translation for an address in a 2-level memory range will provide details of both the "near" and far components. Current exported ADXL components are only for 1-level memory system or for 2nd level memory of 2-level memory system. So add new ADXL components for 1st level memory of 2-level memory system to fully support 2-level memory system and the detection of memory error source(1st level memory or 2nd level memory). Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20210611170123.1057025-2-tony.luck@intel.com
2021-06-18Merge tag 'amd-drm-fixes-5.13-2021-06-16' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixesDave Airlie2-2/+10
amd-drm-fixes-5.13-2021-06-16: amdgpu: - GFX9 and 10 powergating fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210616204913.4368-1-alexander.deucher@amd.com
2021-06-17cxl/pci: Rename CXL REGLOC IDBen Widawsky2-2/+2
The current naming is confusing and wrong. The Register Locator is identified by the DSVSEC identifier, not an offset. Cc: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Link: https://lore.kernel.org/r/20210618003009.956929-1-ben.widawsky@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-06-17cxl/acpi: Use the ACPI CFMWS to create static decoder objectsAlison Schofield1-0/+122
The ACPI CXL Early Discovery Table (CEDT) includes a list of CXL memory resources in CXL Fixed Memory Window Structures (CFMWS). Retrieve each CFMWS in the CEDT and add a cxl_decoder object to the root port (root0) for each memory resource. Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Ben Widawsky <ben.widawsky@intel.com> Link: https://lore.kernel.org/r/d2b73eecfb7ea22e1103f1894b271a89958b4c41.1623968958.git.alison.schofield@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-06-17cxl/acpi: Add the Host Bridge base address to CXL port objectsAlison Schofield1-5/+95
The base address for the Host Bridge port component registers is located in the CXL Host Bridge Structure (CHBS) of the ACPI CXL Early Discovery Table (CEDT). Retrieve the CHBS for each Host Bridge (ACPI0016 device) and include that base address in the port object. Co-developed-by: Vishal Verma <vishal.l.verma@intel.com> Signed-off-by: Vishal Verma <vishal.l.verma@intel.com> Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Ben Widawsky <ben.widawsky@intel.com> Link: https://lore.kernel.org/r/a475ce137b899bc7ae5ba9550b5f198cb29ccbfd.1623968958.git.alison.schofield@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.