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2021-06-03dmaengine: idxd: Fix missing error code in idxd_cdev_open()Jiapeng Chong1-0/+1
The error code is missing in this code scenario, add the error code '-EINVAL' to the return value 'rc'. Eliminate the follow smatch warning: drivers/dma/idxd/cdev.c:113 idxd_cdev_open() warn: missing error code 'rc'. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/1622628446-87909-1-git-send-email-jiapeng.chong@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-06-02drm/i915/dmc: Move struct intel_dmc to intel_dmc.hAnusha Srivatsa2-17/+22
Move struct intel_dmc from i915_drv.h to intel_dmc.h. v2: Add includes along with moving the struct. Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210526220256.4097-4-anusha.srivatsa@intel.com
2021-06-02drm/i915/dmc: Add intel_dmc_has_payload() helperAnusha Srivatsa5-15/+21
We check for dmc_payload being there at various points in the driver. Replace it with the helper. v2: rebased. v3: Move intel_dmc to intel_dmc.h in another patch (Lucas) v4: Remove headers not needed from intel_dmc.h Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210526220256.4097-3-anusha.srivatsa@intel.com
2021-06-02drm/i915/dmc: s/DRM_ERROR/drm_errAnusha Srivatsa1-24/+26
Use new format of debug messages across intel_csr. While at it, change some function definitions which now need dev_priv for drm_err and drm_info etc. v2: use container_of() (Jani) v3: Indentation fixes. (Jani) Cc: Jani Nikula <jani.nikula@linux.intel.com> Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210526220256.4097-2-anusha.srivatsa@intel.com
2021-06-03phy: Sparx5 Eth SerDes: check return value after calling platform_get_resource()Yang Yingliang1-0/+4
It will cause null-ptr-deref if platform_get_resource() returns NULL, we need check the return value. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20210603051014.2674744-1-yangyingliang@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-06-03phy: ralink: phy-mt7621-pci: drop 'of_match_ptr' to fix -Wunused-const-variableSergio Paracuellos1-1/+1
The of_device_id is included unconditionally by of.h header and used in the driver as well. Remove of_match_ptr to fix W=1 compile test warning with !CONFIG_OF: drivers/phy/ralink/phy-mt7621-pci.c:341:34: warning: unused variable 'mt7621_pci_phy_ids' [-Wunused-const-variable] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210603043219.32646-1-sergio.paracuellos@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-06-02scsi: core: Change the type of the second argument of scsi_host_complete_all_commands()Bart Van Assche1-3/+5
Allow the compiler to verify the type of the second argument passed to scsi_host_complete_all_commands(). Link: https://lore.kernel.org/r/20210524025457.11299-4-bvanassche@acm.org Cc: Hannes Reinecke <hare@suse.com> Cc: John Garry <john.garry@huawei.com> Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com> Signed-off-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2021-06-02scsi: core: Introduce enums for the SAM and host status codesBart Van Assche2-2/+2
Make it possible for the compiler to verify whether SAM and host status codes are used correctly. [mkp: resolve conflicts with Hannes' SCSI result series] Link: https://lore.kernel.org/r/20210524025457.11299-3-bvanassche@acm.org Cc: Hannes Reinecke <hare@suse.com> Reviewed-by: John Garry <john.garry@huawei.com> Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com> Signed-off-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2021-06-02of: Merge of_address_to_resource() and of_pci_address_to_resource() implementationsRob Herring1-26/+18
of_address_to_resource() and of_pci_address_to_resource() are almost the same except the former takes an index and the latter takes a BAR number. Now that __of_get_address() can take either one, refactor the functions to use a common implementation. Cc: Frank Rowand <frowand.list@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210527194547.1287934-5-robh@kernel.org
2021-06-02of: address: Use IS_ENABLED() for !CONFIG_PCIRob Herring1-1/+7
Convert address.c to use IS_ENABLED() instead of ifdefs for the public PCI functions. This simplifies the ifdefs in of_address.h. Cc: Frank Rowand <frowand.list@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210527194547.1287934-4-robh@kernel.org
2021-06-02of: Merge of_get_address() and of_get_pci_address() implementationsRob Herring1-49/+13
of_get_address() and of_get_pci_address() are the same implementation except of_get_pci_address() takes the PCI BAR number rather than an index. Modify the of_get_address() implementation to work on either index or BAR and provide wrapper functions for the existing functions. Cc: Frank Rowand <frowand.list@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210527194547.1287934-3-robh@kernel.org
2021-06-02of: Move reserved memory private function declarationsRob Herring2-0/+6
fdt_init_reserved_mem() and fdt_reserved_mem_save_node() are private to the DT code, so move there declarations to of_private.h. There's no need for the dummy functions as CONFIG_OF_RESERVED_MEM is always enabled for CONFIG_OF_EARLY_FLATTREE. Cc: Frank Rowand <frowand.list@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210527193841.1284169-1-robh@kernel.org
2021-06-02of: Drop reserved mem dependency on DMA_DECLARE_COHERENT and DMA_CMARob Herring1-3/+1
Reserved memory regions can be used for more than just DMA regions, so only enabling on DMA_DECLARE_COHERENT (via HAS_DMA) or DMA_CMA is wrong. This effectively doesn't matter except for the few cases arches select NO_DMA. At least, these users of RESERVEDMEM_OF_DECLARE depend on reserved memory support: arch/riscv/mm/init.c:RESERVEDMEM_OF_DECLARE(elfcorehdr, "linux,elfcorehdr", elfcore_hdr_setup); drivers/memory/tegra/tegra210-emc-table.c:RESERVEDMEM_OF_DECLARE(tegra210_emc_table, "nvidia,tegra210-emc-table", drivers/soc/fsl/qbman/bman_ccsr.c:RESERVEDMEM_OF_DECLARE(bman_fbpr, "fsl,bman-fbpr", bman_fbpr); drivers/soc/fsl/qbman/qman_ccsr.c:RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd); drivers/soc/fsl/qbman/qman_ccsr.c:RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr); Let's simplify things and enable OF_RESERVED_MEM when OF_EARLY_FLATTREE is enabled. Cc: Christoph Hellwig <hch@lst.de> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210527223217.1572631-1-robh@kernel.org
2021-06-02Merge branch 'irdma' into rdma.git for-nextJason Gunthorpe90-28900/+33523
Shiraz Saleem says: ==================== Add Intel Ethernet Protocol Driver for RDMA (irdma) The following patch series introduces a unified Intel Ethernet Protocol Driver for RDMA (irdma) for the X722 iWARP device and a new E810 device which supports iWARP and RoCEv2. The irdma module replaces the legacy i40iw module for X722 and extends the ABI already defined for i40iw. It is backward compatible with legacy X722 rdma-core provider (libi40iw). X722 and E810 are PCI network devices that are RDMA capable. The RDMA block of this parent device is represented via an auxiliary device exported to 'irdma' using the core auxiliary bus infrastructure recently added for 5.11 kernel. The parent PCI netdev drivers 'i40e' and 'ice' register auxiliary RDMA devices with private data/ops encapsulated that bind to auxiliary drivers registered in irdma module. Currently, default is RoCEv2 for E810. Runtime support for protocol switch to iWARP will be made available via devlink in a future patch. ==================== Link: https://lore.kernel.org/r/20210602205138.889-1-shiraz.saleem@intel.com Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> * branch 'irdma': RDMA/irdma: Update MAINTAINERS file RDMA/irdma: Add irdma Kconfig/Makefile and remove i40iw RDMA/irdma: Add ABI definitions RDMA/irdma: Add dynamic tracing for CM RDMA/irdma: Add miscellaneous utility definitions RDMA/irdma: Add user/kernel shared libraries RDMA/irdma: Add RoCEv2 UD OP support RDMA/irdma: Implement device supported verb APIs RDMA/irdma: Add PBLE resource manager RDMA/irdma: Add connection manager RDMA/irdma: Add QoS definitions RDMA/irdma: Add privileged UDA queue implementation RDMA/irdma: Add HMC backing store setup functions RDMA/irdma: Implement HW Admin Queue OPs RDMA/irdma: Implement device initialization definitions RDMA/irdma: Register auxiliary driver and implement private channel OPs i40e: Register auxiliary devices to provide RDMA i40e: Prep i40e header for aux bus conversion ice: Register auxiliary device to provide RDMA ice: Implement iidc operations ice: Initialize RDMA support iidc: Introduce iidc.h i40e: Replace one-element array with flexible-array member
2021-06-02RDMA/irdma: Add irdma Kconfig/Makefile and remove i40iwShiraz Saleem34-28858/+41
Add Kconfig and Makefile to build irdma driver. Remove i40iw driver and add an alias in irdma. Remove legacy exported symbols i40e_register_client and i40e_unregister_client from i40e as they are no longer used. irdma is the replacement driver that supports X722. Link: https://lore.kernel.org/r/20210602205138.889-16-shiraz.saleem@intel.com Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02RDMA/irdma: Add dynamic tracing for CMMichael J. Ruhl3-0/+573
Add dynamic tracing functionality to debug connection management issues. Link: https://lore.kernel.org/r/20210602205138.889-14-shiraz.saleem@intel.com Signed-off-by: "Michael J. Ruhl" <michael.j.ruhl@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02RDMA/irdma: Add miscellaneous utility definitionsMustafa Ismail4-0/+2814
Add miscellaneous utility functions and headers. Link: https://lore.kernel.org/r/20210602205138.889-13-shiraz.saleem@intel.com Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02RDMA/irdma: Add user/kernel shared librariesMustafa Ismail2-0/+2121
Building the WQE descriptors for different verb operations are similar in kernel and user-space. Add these shared libraries. Link: https://lore.kernel.org/r/20210602205138.889-12-shiraz.saleem@intel.com Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02RDMA/irdma: Add RoCEv2 UD OP supportMustafa Ismail3-0/+488
Add the header, data structures and functions to populate the WQE descriptors and issue the Control QP commands that support RoCEv2 UD operations. Link: https://lore.kernel.org/r/20210602205138.889-11-shiraz.saleem@intel.com Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02RDMA/irdma: Implement device supported verb APIsMustafa Ismail2-0/+4752
Implement device supported verb APIs. The supported APIs vary based on the underlying transport the ibdev is registered as (i.e. iWARP or RoCEv2). Link: https://lore.kernel.org/r/20210602205138.889-10-shiraz.saleem@intel.com Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02RDMA/irdma: Add PBLE resource managerMustafa Ismail2-0/+657
Implement a Physical Buffer List Entry (PBLE) resource manager to manage a pool of PBLE HMC resource objects. Link: https://lore.kernel.org/r/20210602205138.889-9-shiraz.saleem@intel.com Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02RDMA/irdma: Add connection managerMustafa Ismail2-0/+4838
Add connection management (CM) implementation for iWARP including accept, reject, connect, create_listen, destroy_listen and CM utility functions Link: https://lore.kernel.org/r/20210602205138.889-8-shiraz.saleem@intel.com Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02RDMA/irdma: Add QoS definitionsMustafa Ismail2-0/+447
Add definitions for managing the RDMA HW work scheduler (WS) tree. A WS node is created via a control QP operation with the bandwidth allocation, arbitration scheme, and traffic class of the QP specified. The Qset handle returned associates the QoS parameters for the QP. The Qset is registered with the LAN and an equivalent node is created in the LAN packet scheduler tree. Link: https://lore.kernel.org/r/20210602205138.889-7-shiraz.saleem@intel.com Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02RDMA/irdma: Add privileged UDA queue implementationMustafa Ismail2-0/+1939
Implement privileged UDA queues to handle iWARP connection packets and receive exceptions. Link: https://lore.kernel.org/r/20210602205138.889-6-shiraz.saleem@intel.com Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02RDMA/irdma: Add HMC backing store setup functionsMustafa Ismail2-0/+890
HW uses host memory as a backing store for a number of protocol context objects and queue state tracking. The Host Memory Cache (HMC) is a component responsible for managing these objects stored in host memory. Add the functions and data structures to manage the allocation of backing pages used by the HMC for the various objects Link: https://lore.kernel.org/r/20210602205138.889-5-shiraz.saleem@intel.com Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02RDMA/irdma: Implement HW Admin Queue OPsMustafa Ismail4-0/+8506
The driver posts privileged commands to the HW Admin Queue (Control QP or CQP) to request administrative actions from the HW. Implement create/destroy of CQP and the supporting functions, data structures and headers to handle the different CQP commands Link: https://lore.kernel.org/r/20210602205138.889-4-shiraz.saleem@intel.com Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02RDMA/irdma: Implement device initialization definitionsMustafa Ismail5-0/+3321
Implement device initialization routines, interrupt set-up, and allocate object bit-map tracking structures. Also, add device specific attributes and register definitions. Link: https://lore.kernel.org/r/20210602205138.889-3-shiraz.saleem@intel.com [flexible array transformation] Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02RDMA/irdma: Register auxiliary driver and implement private channel OPsMustafa Ismail3-0/+1129
Register auxiliary drivers which can attach to auxiliary RDMA devices from Intel PCI netdev drivers i40e and ice. Implement the private channel ops, and register net notifiers. Link: https://lore.kernel.org/r/20210602205138.889-2-shiraz.saleem@intel.com [flexible array transformation] Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-02amd/display: convert DRM_DEBUG_ATOMIC to drm_dbg_atomicSimon Ser1-1/+1
This allows to tie the log message to a specific DRM device. Signed-off-by: Simon Ser <contact@emersion.fr> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-02drm/amdgpu: make sure we unpin the UVD BONirmoy Das1-0/+1
Releasing pinned BOs is illegal now. UVD 6 was missing from: commit 2f40801dc553 ("drm/amdgpu: make sure we unpin the UVD BO") Fixes: 2f40801dc553 ("drm/amdgpu: make sure we unpin the UVD BO") Cc: stable@vger.kernel.org Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-02drm/amd/amdgpu:save psp ring wptr to avoid attackVictor Zhao3-2/+5
[Why] When some tools performing psp mailbox attack, the readback value of register can be a random value which may break psp. [How] Use a psp wptr cache machanism to aovid the change made by attack. v2: unify change and add detailed reason Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-02drm/amd/display: Fix potential memory leak in DMUB hw_initRoman Li1-2/+2
[Why] On resume we perform DMUB hw_init which allocates memory: dm_resume->dm_dmub_hw_init->dc_dmub_srv_create->kzalloc That results in memory leak in suspend/resume scenarios. [How] Allocate memory for the DC wrapper to DMUB only if it was not allocated before. No need to reallocate it on suspend/resume. Signed-off-by: Lang Yu <Lang.Yu@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-02drm/amdgpu: Don't query CE and UE errorsLuben Tuikov1-16/+0
On QUERY2 IOCTL don't query counts of correctable and uncorrectable errors, since when RAS is enabled and supported on Vega20 server boards, this takes insurmountably long time, in O(n^3), which slows the system down to the point of it being unusable when we have GUI up. Fixes: ae363a212b14 ("drm/amdgpu: Add a new flag to AMDGPU_CTX_OP_QUERY_STATE2") Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-02drm/amd/display: Fix overlay validation by considering cursorsRodrigo Siqueira1-1/+9
A few weeks ago, we saw a two cursor issue in a ChromeOS system. We fixed it in the commit: drm/amd/display: Fix two cursor duplication when using overlay (read the commit message for more details) After this change, we noticed that some IGT subtests related to kms_plane and kms_plane_scaling started to fail. After investigating this issue, we noticed that all subtests that fail have a primary plane covering the overlay plane, which is currently rejected by amdgpu dm. Fail those IGT tests highlight that our verification was too broad and compromises the overlay usage in our drive. This patch fixes this issue by ensuring that we only reject commits where the primary plane is not fully covered by the overlay when the cursor hardware is enabled. With this fix, all IGT tests start to pass again, which means our overlay support works as expected. Cc: Tianci.Yin <tianci.yin@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Nicholas Choi <nicholas.choi@amd.com> Cc: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Mark Yacoub <markyacoub@google.com> Cc: Daniel Wheeler <daniel.wheeler@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-02drm/amdgpu: refine amdgpu_fru_get_product_infoJiansong Chen1-19/+23
1. eliminate potential array index out of bounds. 2. return meaningful value for failure. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Jack Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-02drm/amdgpu: add judgement for dc supportAsher Song1-1/+3
Drop DC initialization when DCN is harvested in VBIOS. The way doesn't affect virtual display ip initialization. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Asher Song <Asher.Song@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-02drm/amd/display: Fix GPU scaling regression by FS video supportNicholas Kazlauskas1-7/+7
[Why] FS video support regressed GPU scaling and the scaled buffer ends up stuck in the top left of the screen at native size - full, aspect, center scaling modes do not function. This is because decide_crtc_timing_for_drm_display_mode() does not get called when scaling is enabled. [How] Split recalculate timing and scaling into two different flags. We don't want to call drm_mode_set_crtcinfo() for scaling, but we do want to call it for FS video. Optimize and move preferred_refresh calculation next to decide_crtc_timing_for_drm_display_mode() like it used to be since that's not used for FS video. We don't need to copy over the VIC or polarity in the case of FS video modes because those don't change. Fixes: 6f59f229f8ed7a ("drm/amd/display: Skip modeset for front porch change") Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-02drm/amd/display: Allow bandwidth validation for 0 streams.Bindu Ramamurthy1-1/+1
[Why] Bandwidth calculations are triggered for non zero streams, and in case of 0 streams, these calculations were skipped with pstate status not being updated. [How] As the pstate status is applicable for non zero streams, check added for allowing 0 streams inline with dcn internal bandwidth validations. Signed-off-by: Bindu Ramamurthy <bindu.r@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-02netdevsim: Allow setting parent node of rate objectsDmytro Linkin2-4/+89
Implement new devlink ops that allow setting rate node as a parent for devlink port (leaf) or another devlink node through devlink API. Expose parent names to netdevsim debugfs in read only mode. Co-developed-by: Vlad Buslov <vladbu@nvidia.com> Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Signed-off-by: Dmytro Linkin <dlinkin@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-02netdevsim: Implement support for devlink rate nodesDmytro Linkin2-0/+81
Implement new devlink ops that allow creation, deletion and setting of shared/max tx rate of devlink rate nodes through devlink API. Expose rate node and it's tx rates to netdevsim debugfs. Co-developed-by: Vlad Buslov <vladbu@nvidia.com> Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Signed-off-by: Dmytro Linkin <dlinkin@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-02netdevsim: Implement devlink rate leafs tx rate supportDmytro Linkin1-3/+75
Implement new devlink ops that allow shared and max tx rate control for devlink port rate objects (leafs) through devlink API. Expose rate values of VF ports to netdevsim debugfs. Co-developed-by: Vlad Buslov <vladbu@nvidia.com> Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Signed-off-by: Dmytro Linkin <dlinkin@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-02netdevsim: Register devlink rate leaf objects per VFDmytro Linkin1-0/+11
Register devlink rate leaf objects per VF. Co-developed-by: Vlad Buslov <vladbu@nvidia.com> Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Signed-off-by: Dmytro Linkin <dlinkin@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-02netdevsim: Implement legacy/switchdev mode for VFsDmytro Linkin4-1/+104
Implement callbacks to set/get eswitch mode value. Add helpers to check current mode. Instantiate VFs' net devices and devlink ports on switchdev enabling and remove them on legacy enabling. Changing number of VFs while in switchdev mode triggers VFs creation/deletion. Also disable NDO API callback to set VF rate, since it's legacy API. Switchdev API to set VF rate will be implemented in one of the next patches. Signed-off-by: Dmytro Linkin <dlinkin@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-02netdevsim: Implement VFsDmytro Linkin2-27/+77
Allow creation of netdevsim ports for VFs along with allocations of corresponding net devices and devlink ports. Add enums and helpers to distinguish PFs' ports from VFs' ports. Ports creation/deletion debugfs API intended to be used with physical ports only. VFs instantiation will be done in one of the next patches. Signed-off-by: Dmytro Linkin <dlinkin@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-02netdevsim: Implement port types and indexingDmytro Linkin3-12/+60
Define type of ports, which netdevsim driver currently operates with as PF. Define new port type - VF, which will be implemented in following patches. Add helper functions to distinguish them. Add helper function to get VF index from port index. Add port indexing logic where PFs' indexes starts from 0, VFs' - from NSIM_DEV_VF_PORT_INDEX_BASE. All ports uses same index pool, which means that PF port may be created with index from VFs' indexes range. Maximum number of VFs, which the driver can allocate, is limited by UINT_MAX - BASE. Signed-off-by: Dmytro Linkin <dlinkin@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-02netdevsim: Disable VFs on nsim_dev_reload_destroy() callDmytro Linkin3-4/+8
Move VFs disabling from device release() to nsim_dev_reload_destroy() to make VFs disabling and ports removal simultaneous. This is a requirement for VFs ports implemented in next patches. Signed-off-by: Dmytro Linkin <dlinkin@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-02netdevsim: Add max_vfs to bus_devDmytro Linkin3-8/+112
Currently there is no limit to the number of VFs netdevsim can enable. In a real systems this value exist and used by the driver. Fore example, some features might need to consider this value when allocating memory. Expose max_vfs variable to debugfs as configurable resource. If are VFs configured (num_vfs != 0) then changing of max_vfs not allowed. Co-developed-by: Yuval Avnery <yuvalav@nvidia.com> Signed-off-by: Yuval Avnery <yuvalav@nvidia.com> Signed-off-by: Dmytro Linkin <dlinkin@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-02nfp: flower-ct: add tc merge functionalityLouis Peens1-4/+158
Add merging of pre/post_ct flow rules into the tc_merge table. Pre_ct flows needs to be merge with post_ct flows and vice versa. This needs to be done for all flows in the same zone table, as well as with the wc_zone_table, which is for flows masking out ct_zone info. Cleanup is happening when all the tables are cleared up and prints a warning traceback as this is not expected in the final version. At this point we are not actually returning success for the offload, so we do not get any delete requests for flows, so we can't delete them that way yet. This means that cleanup happens in what would usually be an exception path. Signed-off-by: Louis Peens <louis.peens@corigine.com> Signed-off-by: Yinjun Zhang <yinjun.zhang@corigine.com> Signed-off-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-02nfp: flower-ct: add tc_merge_tbLouis Peens3-0/+47
Add the table required to store the merge result of pre_ct and post_ct flows. This is just the initial setup and teardown of the table, the implementation will be in follow-up patches. Signed-off-by: Louis Peens <louis.peens@corigine.com> Signed-off-by: Yinjun Zhang <yinjun.zhang@corigine.com> Signed-off-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-02nfp: flower-ct: add a table to map flow cookies to ct flowsLouis Peens4-7/+89
Add a hashtable which contains entries to map flow cookies to ct flow entries. Currently the entries are added and not used, but follow-up patches will use this for stats updates and flow deletes. Signed-off-by: Louis Peens <louis.peens@corigine.com> Signed-off-by: Yinjun Zhang <yinjun.zhang@corigine.com> Signed-off-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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