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2015-04-10drm/i915: Free batch pool when idleChris Wilson1-1/+12
2015-04-10drm/i915: Split the batch pool by engineChris Wilson9-27/+35
2015-04-10drm/i915: Tidy batch pool logicChris Wilson3-37/+27
2015-04-10drm/i915: Split i915_gem_batch_pool into its own headerChris Wilson3-12/+44
2015-04-10drm/i915: Re-enable RPS wait-boosting for all enginesChris Wilson1-1/+1
2015-04-10drm/i915: Deminish contribution of wait-boosting from clientsChris Wilson5-34/+70
2015-04-10drm/i915: Boost GPU frequency if we detect outstanding pageflipsChris Wilson3-3/+45
2015-04-10drm/i915: Fix computation of last_adjustment for RPS autotuningChris Wilson1-15/+12
2015-04-10drm/i915: Agressive downclocking on BaytrailChris Wilson4-5/+12
2015-04-10drm/i915: Fix the flip synchronisation to consider mmioflipsChris Wilson1-2/+11
2015-04-10drm/i915: Cache last obj->pages location for i915_gem_object_get_page()Chris Wilson2-5/+30
2015-04-10drm/i915/skl: Implement WaDisableVFUnitClockGatingDamien Lespiau2-0/+5
2015-04-10drm/i915/skl: Fix stepping check for a couple of W/AsDamien Lespiau1-1/+1
2015-04-10drm/i915: Do not set L3-LLC Coherency bit in ctx descriptorArun Siluvery1-1/+2
2015-04-10drm/i915: use kref_put_mutex in i915_gem_request_unreference__unlockedMaarten Lankhorst1-6/+6
2015-04-10drm/i915: Don't use staged config in intel_mst_pre_enable_dp()Ander Conselvan de Oliveira1-4/+4
2015-04-10drm/i915: Don't use staged config in check_encoder_cloning()Ander Conselvan de Oliveira1-10/+25
2015-04-10drm/i915: Don't use staged config in check_digital_port_conflicts()Ander Conselvan de Oliveira1-8/+14
2015-04-10drm/i915: Remove intel_crtc->new_configAnder Conselvan de Oliveira2-32/+0
2015-04-10drm/i915: Don't use intel_crtc->new_config in pll calculation codeAnder Conselvan de Oliveira1-4/+11
2015-04-10drm/i915: Don't use staged config for VLV cdclk calculationsAnder Conselvan de Oliveira1-14/+41
2015-04-10drm/i915: Silence a sparse warningVille Syrjälä1-1/+1
2015-04-10drm/i915: Allow disabling the destination colorkey for overlayChris Wilson2-11/+20
2015-04-07drm/i915: add i915 specific connector debugfs file for DPCDJani Nikula3-0/+99
2015-04-07drm/i915/bdw: WaProgramL3SqcReg1DefaultRodrigo Vivi2-0/+6
2015-04-07drm/i915/skl: Enabling PSR2 SU with frame syncSonika Jindal4-1/+68
2015-04-01drm/i915: Make debugfs/i915_gem_request more friendlyChris Wilson1-13/+26
2015-04-01drm/i915: Set best_encoder field of connector_state also when disablingAnder Conselvan de Oliveira1-0/+1
2015-04-01drm/i915: base gmbus pin validity check on the gmbus pin map arrayJani Nikula6-12/+17
2015-04-01drm/i915: index gmbus tables using the pin pair numberJani Nikula3-30/+40
2015-04-01drm/i915: refer to pin instead of port in the intel_i2c.c interfacesJani Nikula6-12/+12
2015-04-01drm/i915: rename GMBUS_PORT_* macros as GMBUS_PIN_*Jani Nikula8-23/+23
2015-04-01drm/i915: Fix for ringbuf space wait in LRC modeJohn Harrison2-8/+12
2015-04-01drm/i915: Move common request allocation code into a common functionJohn Harrison6-56/+54
2015-04-01drm/i915: Make intel_logical_ring_begin() staticJohn Harrison2-240/+237
2015-04-01drm/i915: Rename 'do_execbuf' to 'execbuf_submit'John Harrison3-12/+12
2015-03-31drm/i915: Convert the ddi cdclk code to get_display_clock_speedVille Syrjälä6-105/+102
2015-03-31drm/i915: Simplify ilk_get_aux_clock_dividerVille Syrjälä1-4/+2
2015-03-31drm/i915: Assume 400MHz cdclk for the rest of gen4-7Ville Syrjälä1-1/+2
2015-03-31drm/i915: ILK cdclk seems to be 450MHzVille Syrjälä1-0/+8
2015-03-31drm/i915: Return more precise cdclk for gen2/3Ville Syrjälä1-11/+11
2015-03-31drm/i915: Enable DVO 2x clock around DVO encoder initVille Syrjälä1-0/+17
2015-03-31drm/i915: Mark the overlay active only if we got ring spaceVille Syrjälä1-2/+2
2015-03-31drm/i915: Convert overlay->{active, pfit_active} to boolsVille Syrjälä1-6/+6
2015-03-31drm/i915: Convert BUGs to WARNs in the video overlay codeVille Syrjälä1-11/+11
2015-03-31drm/i915/chv: Remove Wait for a previous gfx force-offDeepak S1-2/+4
2015-03-30drm/i915: PSR: Keep sink state consistent with sourceDurgadoss R1-1/+1
2015-03-30Enabled dithering in the intel VCH DVO for 18bpp pipelines.Thomas Richter1-3/+18
2015-03-30drm/i915: Add i915_gem_request_unreference__unlockedChris Wilson2-6/+15
2015-03-30drm/i915: Check lane sharing between pipes B & C using atomic stateAnder Conselvan de Oliveira1-27/+42
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