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path: root/include/asm-mips/cpu-features.h (follow)
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2007-12-01[MIPS] Fix use of smp_processor_id() in preemptible code.Pavel Kiryukhin1-3/+3
Freeing prom memory: 956kb freed Freeing firmware memory: 978944k freed Freeing unused kernel memory: 180k freed BUG: using smp_processor_id() in preemptible [00000000] code: swapper/1 caller is r4k_dma_cache_wback_inv+0x144/0x2a0 Call Trace: [<80117af8>] r4k_dma_cache_wback_inv+0x144/0x2a0 [<802e4b84>] debug_smp_processor_id+0xd4/0xf0 [<802e4b7c>] debug_smp_processor_id+0xcc/0xf0 ... CONFIG_DEBUG_PREEMPT is enabled. -- Bug cause is blast_dcache_range() in preemptible code [in r4k_dma_cache_wback_inv()]. blast_dcache_range() is constructed via __BUILD_BLAST_CACHE_RANGE that uses cpu_dcache_line_size(). It uses current_cpu_data that use smp_processor_id() in turn. In case of CONFIG_DEBUG_PREEMPT smp_processor_id emits BUG if we are executing with preemption enabled. Cpu options of cpu0 are assumed to be the superset of all processors. Can I make the same assumptions for cache line size and fix this issue the following way: Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle1-1/+4
This saves a few k on systems which only ever ship with a single CPU type. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle1-3/+0
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] Enable support for the userlocal hardware registerRalf Baechle1-0/+4
Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-03-17[MIPS] FPU ownership management & preemption fixesAtsushi Nemoto1-0/+3
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13[MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle1-2/+2
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13[MIPS] Default cpu_has_mipsmt to a runtime checkChris Dearman1-5/+1
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29[MIPS] Fix configuration of R2 CPU features and multithreading.Ralf Baechle1-12/+8
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-26Don't include linux/config.h from anywhere else in include/David Woodhouse1-1/+0
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-04-19[MIPS] FPU affinity for MT ASE.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-18[MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto1-0/+3
If dcache_size != icache_size or dcache_size != scache_size, or set-associative cache, icache/scache does not flushed properly. Make blast_?cache_page_indexed() masks its index value correctly. Also, use physical address for physically indexed pcache/scache. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10MIPS: Reorganize ISA constants strictly as bitmasks.Ralf Baechle1-24/+21
Signed-off-by: Ralf Baechle <ralf@ongar.mips.com>
2006-01-10MIPS: Introduce machinery for testing for MIPSxxR1/2.Ralf Baechle1-0/+24
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle1-2/+13
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Detect the MIPS R2 vectored interrupt, external interrupt controllerRalf Baechle1-0/+24
options and the precense of the MT ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Redo RM9000 workaround which along with other DSP ASE changes wasRalf Baechle1-11/+0
causing some headache for debuggers knowing about signal frames. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Support the MIPS32 / MIPS64 DSP ASE.Ralf Baechle1-0/+4
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Cleanup decoding of MIPSxx config registers.Ralf Baechle1-3/+13
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-09-05[PATCH] mips: clean up 32/64-bit configurationRalf Baechle1-2/+2
Start cleaning 32-bit vs. 64-bit configuration. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16Linux-2.6.12-rc2Linus Torvalds1-0/+159
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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