linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2007-07-10	[MIPS] Enable support for the userlocal hardware register	Ralf Baechle	1	-0/+4
	Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-03-17	[MIPS] FPU ownership management & preemption fixes	Atsushi Nemoto	1	-0/+3
	Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13	[MIPS] Use the proper technical term for naming some of the cache macros.	Ralf Baechle	1	-2/+2
	Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13	[MIPS] Default cpu_has_mipsmt to a runtime check	Chris Dearman	1	-5/+1
	Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29	[MIPS] Fix configuration of R2 CPU features and multithreading.	Ralf Baechle	1	-12/+8
	Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-26	Don't include linux/config.h from anywhere else in include/	David Woodhouse	1	-1/+0
	Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-04-19	[MIPS] FPU affinity for MT ASE.	Ralf Baechle	1	-1/+1
	Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-18	[MIPS] local_r4k_flush_cache_page fix	Atsushi Nemoto	1	-0/+3
	If dcache_size != icache_size or dcache_size != scache_size, or set-associative cache, icache/scache does not flushed properly. Make blast_?cache_page_indexed() masks its index value correctly. Also, use physical address for physically indexed pcache/scache. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10	MIPS: Reorganize ISA constants strictly as bitmasks.	Ralf Baechle	1	-24/+21
	Signed-off-by: Ralf Baechle <ralf@ongar.mips.com>
2006-01-10	MIPS: Introduce machinery for testing for MIPSxxR1/2.	Ralf Baechle	1	-0/+24
	Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29	Cleanup the mess in cpu_cache_init.	Ralf Baechle	1	-2/+13
	Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29	Detect the MIPS R2 vectored interrupt, external interrupt controller	Ralf Baechle	1	-0/+24
	options and the precense of the MT ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29	Redo RM9000 workaround which along with other DSP ASE changes was	Ralf Baechle	1	-11/+0
	causing some headache for debuggers knowing about signal frames. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29	Support the MIPS32 / MIPS64 DSP ASE.	Ralf Baechle	1	-0/+4
	Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29	Cleanup decoding of MIPSxx config registers.	Ralf Baechle	1	-3/+13
	Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-09-05	[PATCH] mips: clean up 32/64-bit configuration	Ralf Baechle	1	-2/+2
	Start cleaning 32-bit vs. 64-bit configuration. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16	Linux-2.6.12-rc2	Linus Torvalds	1	-0/+159
	Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!