linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2006-06-29	[PATCH] genirq: add ->retrigger() irq op to consolidate hw_irq_resend()	Ingo Molnar	1	-9/+0
	Add ->retrigger() irq op to consolidate hw_irq_resend() implementations. (Most architectures had it defined to NOP anyway.) NOTE: ia64 needs testing. i386 and x86_64 tested. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-27	[PATCH] x86: increase interrupt vector range	Rusty Russell	1	-1/+1
	Remove the limit of 256 interrupt vectors by changing the value stored in orig_{e,r}ax to be the complemented interrupt vector. The orig_{e,r}ax needs to be < 0 to allow the signal code to distinguish between return from interrupt and return from syscall. With this change applied, NR_IRQS can be > 256. Xen extends the IRQ numbering space to include room for dynamically allocated virtual interrupts (in the range 256-511), which requires a more permissive interface to do_IRQ. Signed-off-by: Ian Pratt <ian.pratt@xensource.com> Signed-off-by: Christian Limpach <Christian.Limpach@cl.cam.ac.uk> Signed-off-by: Chris Wright <chrisw@sous-sol.org> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com> Cc: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26	[PATCH] x86_64: Remove long obsolete CVS	Andi Kleen	1	-2/+0
	Early development of x86-64 Linux was in CVS, but that hasn't been the case for a long time now. Remove the obsolete $Id$s. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-04-26	Don't include linux/config.h from anywhere else in include/	David Woodhouse	1	-1/+0
	Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-01-11	[PATCH] x86_64: Remove useless KDB vector	Andi Kleen	1	-1/+2
	It was set as an NMI, but the NMI bit always forces an interrupt to end up at vector 2. So it was never used. Remove. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-11	[PATCH] x86_64: Don't claim too many vectors for TLB flushing	Jason Uhlenkott	1	-4/+3
	It looks like the new scalable TLB flush code for x86_64 is claiming one more IRQ vector than it actually uses. Signed-off-by: Jason Uhlenkott <jasonuhl@sgi.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-14	[PATCH] x86_64: Support for AMD specific MCE Threshold.	Jacob Shin	1	-1/+1
	MC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F. This register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations. The user may interface through sysfs files in order to change the threshold configuration. bank%d/error_count - reads current error count, write to clear. bank%d/interrupt_enable - set/clear interrupt enable. bank%d/threshold_limit - read/write the threshold limit. APIC vector 0xF9 in hw_irq.h. 5 software defined bank ids in mce.h. new apic.c function to setup threshold apic lvt. defaults to interrupt off, count enabled, and threshold limit max. sysfs interface created on /sys/devices/system/threshold. AK: added some ifdefs to make it compile on UP Signed-off-by: Jacob Shin <jacob.shin@amd.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-12	[PATCH] x86-64: Declare NMI_VECTOR and handle it in the IPI sending code.	Jan Beulich	1	-0/+1
	Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-12	[PATCH] x86-64: Make remote TLB flush more scalable	Andi Kleen	1	-8/+9
	Instead of using a global spinlock to protect the state of the remote TLB flush use a lock and state for each sending CPU. To tell the receiver where to look for the state use 8 different call vectors. Each CPU uses a specific vector to trigger flushes on other CPUs. Depending on the received vector the target CPUs look into the right per cpu variable for the flush data. When the system has more than 8 CPUs they are hashed to the 8 available vectors. The limited global vector space forces us to this right now. In future when interrupts are split into per CPU domains this could be fixed, at the cost of needing more IPIs in flat mode. Also some minor cleanup in the smp flush code and remove some outdated debug code. Requires patch to move cpu_possible_map setup earlier. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16	Linux-2.6.12-rc2	Linus Torvalds	1	-0/+144
	Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!