| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
Add dt-bindings for the audio memory arbiter found on Amlogic's
A113 based SoCs
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
Add SDM845 AOSS (always on subsystem) reset controller binding
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
* clk-davinci-psc-da830:
clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration
* clk-renesas:
clk: renesas: cpg-mssr: Add support for R-Car E3
clk: renesas: Add r8a77990 CPG Core Clock Definitions
clk: renesas: rcar-gen2: Centralize quirks handling
clk: renesas: r8a77980: Correct parent clock of PCIEC0
clk: renesas: r8a7794: Fix LB clock divider
clk: renesas: r8a7792: Fix LB clock divider
clk: renesas: r8a7791/r8a7793: Fix LB clock divider
clk: renesas: r8a7745: Fix LB clock divider
clk: renesas: r8a7743: Fix LB clock divider
clk: renesas: cpg-mssr: Add r8a77470 support
clk: renesas: Add r8a77470 CPG Core Clock Definitions
clk: renesas: r8a77965: Add MSIOF controller clocks
* clk-at91-recalc:
clk: at91: PLL recalc_rate() now using cached MUL and DIV values
* clk-davinci:
clk: davinci: Fix link errors when not all SoCs are enabled
clk: davinci: psc: allow for dev == NULL
clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLARE
clk: davinci: pll: allow dev == NULL
clk: davinci: psc-dm365: fix few clocks
clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled
clk: davinci: psc-dm355: fix ASP0/1 clkdev lookups
clk: davinci: pll-dm355: fix SYSCLKn parent names
clk: davinci: pll-dm355: drop pll2_sysclk2
* clk-meson:
clk: meson: axg: let mpll clocks round closest
clk: meson: mpll: add round closest support
clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL
clk: meson: use SPDX license identifiers consistently
clk: meson: drop CLK_SET_RATE_PARENT flag
clk: meson-axg: Add AO Clock and Reset controller driver
clk: meson: aoclk: refactor common code into dedicated file
clk: meson: migrate to devm_of_clk_add_hw_provider API
clk: meson: gxbb: add the video decoder clocks
clk: meson: meson8b: add support for the NAND clocks
dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
dt-bindings: clock: meson8b: export the NAND clock
|
|
* clk-allwinner:
clk: sunxi-ng: r40: export a regmap to access the GMAC register
clk: sunxi-ng: r40: rewrite init code to a platform driver
clk: sunxi-ng: add support for H6 PRCM CCU
* clk-rockchip:
clk: rockchip: remove deprecated gate-clk code and dt-binding
clk: rockchip: use match_string() helper
* clk-tegra:
clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
clk: tegra20: Correct parents of CDEV1/2 clocks
clk: tegra20: Add DEV1/DEV2 OSC dividers
* clk-berlin:
clk: berlin: switch to SPDX license identifier
* clk-qcom-mmagic:
clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled
clk: qcom: Register the gdscs before the clocks
clk: qcom: gdsc: Add support for ALWAYS_ON gdscs
|
|
Just add binding for a required reset referenced by Mali-450 on MT7623
or MT2701 SoC.
Cc: devicetree@vger.kernel.org
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Add dt-bindings headers for the Meson-AXG's AO clock and
reset controller.
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
|
The H6 has clock/reset controls in PRCM part, like old SoCs such as H3
and A64. However, the PRCM CCU is rearranged; the register arragement
is now similar to the main CCU of H6, and the PRCM now has two APB
buses to control -- one is clocked from AHB clock derivde from AR100
clock, the other is clocked from the same mux with AR100 clock.
Therefore a new driver is written for it.
As there's no official document about the PRCM in H6, all the information
are indirectly collected from BSP and parts of the document, and the
information source is noted as comments in the driver's source code. If
reliable information is provided furtherly, the driver needs to be
rechecked.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
|
Pull clk updates from Stephen Boyd:
"The large diff this time around is from the addition of a new clk
driver for the TI Davinci family of SoCs. So far those clks have been
supported with a custom implementation of the clk API in the arch port
instead of in the CCF. With this driver merged we're one step closer
to having a single clk API implementation.
The other large diff is from the Amlogic clk driver that underwent
some major surgery to use regmap. Beyond that, the biggest hitter is
Samsung which needed some reworks to properly handle clk provider
power domains and a bunch of PLL rate updates.
The core framework was fairly quiet this round, just getting some
cleanups and small fixes for some of the more esoteric features. And
the usual set of driver non-critical fixes, cleanups, and minor
additions are here as well.
Core:
- Rejig clk_ops::init() to be a little earlier for phase/accuracy ops
- debugfs ops macroized to shave some lines of boilerplate code
- Always calculate the phase instead of caching it in clk_get_phase()
- More __must_check on bulk clk APIs
New Drivers:
- TI's Davinci family of SoCs
- Intel's Stratix10 SoC
- stm32mp157 SoC
- Allwinner H6 CCU
- Silicon Labs SI544 clock generator chip
- Renesas R-Car M3-N and V3H SoCs
- i.MX6SLL SoCs
Removed Drivers:
- ST-Ericsson AB8540/9540
Updates:
- Mediatek MT2701 and MT7622 audsys support and MT2712 updates
- STM32F469 DSI and STM32F769 sdmmc2 support
- GPIO clks can sleep now
- Spreadtrum SC9860 RTC clks
- Nvidia Tegra MBIST workarounds and various minor fixes
- Rockchip phase handling fixes and a memory leak plugged
- Renesas drivers switch to readl/writel from clk_readl/clk_writel
- Renesas gained CPU (Z/Z2) and watchdog support
- Rockchip rk3328 display clks and rk3399 1.6GHz PLL support
- Qualcomm PM8921 PMIC XO buffers
- Amlogic migrates to regmap APIs
- TI Keystone clk latching support
- Allwinner H3 and H5 video clk fixes
- Broadcom BCM2835 PLLs needed another bit to enable
- i.MX6SX CKO mux fix and i.MX7D Video PLL divider fix
- i.MX6UL/ULL epdc_podf support
- Hi3798CV200 COMBPHY0 and USB2_OTG_UTMI and phase support for eMMC"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (233 commits)
clk: davinci: add a reset lookup table for psc0
clk: imx: add clock driver for imx6sll
dt-bindings: imx: update clock doc for imx6sll
clk: imx: add new gate/gate2 wrapper funtion
clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux
clk: cs2000: set pm_ops in hibernate-compatible way
clk: bcm2835: De-assert/assert PLL reset signal when appropriate
clk: imx7d: Move clks_init_on before any clock operations
clk: imx7d: Correct ahb clk parent select
clk: imx7d: Correct dram pll type
clk: imx7d: Add USB clock information
clk: socfpga: stratix10: add clock driver for Stratix10 platform
dt-bindings: documentation: add clock bindings information for Stratix10
clk: ti: fix flag space conflict with clkctrl clocks
clk: uniphier: add additional ethernet clock lines for Pro4
clk: uniphier: add SATA clock control support
clk: uniphier: add PCIe clock control support
clk: Add driver for the si544 clock generator chip
clk: davinci: Remove redundant dev_err calls
clk: uniphier: add ethernet clock control support for PXs3
...
|
|
Pull ARM SoC driver updates from Arnd Bergmann:
"The main addition this time around is the new ARM "SCMI" framework,
which is the latest in a series of standards coming from ARM to do
power management in a platform independent way.
This has been through many review cycles, and it relies on a rather
interesting way of using the mailbox subsystem, but in the end I
agreed that Sudeep's version was the best we could do after all.
Other changes include:
- the ARM CCN driver is moved out of drivers/bus into drivers/perf,
which makes more sense. Similarly, the performance monitoring
portion of the CCI driver are moved the same way and cleaned up a
little more.
- a series of updates to the SCPI framework
- support for the Mediatek mt7623a SoC in drivers/soc
- support for additional NVIDIA Tegra hardware in drivers/soc
- a new reset driver for Socionext Uniphier
- lesser bug fixes in drivers/soc, drivers/tee, drivers/memory, and
drivers/firmware and drivers/reset across platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (87 commits)
reset: uniphier: add ethernet reset control support for PXs3
reset: stm32mp1: Enable stm32mp1 reset driver
dt-bindings: reset: add STM32MP1 resets
reset: uniphier: add Pro4/Pro5/PXs2 audio systems reset control
reset: imx7: add 'depends on HAS_IOMEM' to fix unmet dependency
reset: modify the way reset lookup works for board files
reset: add support for non-DT systems
clk: scmi: use devm_of_clk_add_hw_provider() API and drop scmi_clocks_remove
firmware: arm_scmi: prevent accessing rate_discrete uninitialized
hwmon: (scmi) return -EINVAL when sensor information is unavailable
amlogic: meson-gx-socinfo: Update soc ids
soc/tegra: pmc: Use the new reset APIs to manage reset controllers
soc: mediatek: update power domain data of MT2712
dt-bindings: soc: update MT2712 power dt-bindings
cpufreq: scmi: add thermal dependency
soc: mediatek: fix the mistaken pointer accessed when subdomains are added
soc: mediatek: add SCPSYS power domain driver for MediaTek MT7623A SoC
soc: mediatek: avoid hardcoded value with bus_prot_mask
dt-bindings: soc: add header files required for MT7623A SCPSYS dt-binding
dt-bindings: soc: add SCPSYS binding for MT7623 and MT7623A SoC
...
|
|
This patch adds the reset binding entry for STM32MP1
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
The Allwinner H6 SoC has a CCU which has been largely rearranged.
Add support for it in the sunxi-ng CCU framework.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
|
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
Add DT bindings for the Meson-AXG SoC Reset Controller include file,
and also slightly update documentation.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
Pull ARM SoC driver updates from Arnd Bergmann:
"This branch contains platform-related driver updates for ARM and
ARM64, these are the areas that bring the changes:
New drivers:
- driver support for Renesas R-Car V3M (R8A77970)
- power management support for Amlogic GX
- a new driver for the Tegra BPMP thermal sensor
- a new bus driver for Technologic Systems NBUS
Changes for subsystems that prefer to merge through arm-soc:
- the usual updates for reset controller drivers from Philipp Zabel,
with five added drivers for SoCs in the arc, meson, socfpa,
uniphier and mediatek families
- updates to the ARM SCPI and PSCI frameworks, from Sudeep Holla,
Heiner Kallweit and Lorenzo Pieralisi
Changes specific to some ARM-based SoC
- the Freescale/NXP DPAA QBMan drivers from PowerPC can now work on
ARM as well
- several changes for power management on Broadcom SoCs
- various improvements on Qualcomm, Broadcom, Amlogic, Atmel,
Mediatek
- minor Cleanups for Samsung, TI OMAP SoCs"
[ NOTE! This doesn't work without the previous ARM SoC device-tree pull,
because the R8A77970 driver is missing a header file that came from
that pull.
The fact that this got merged afterwards only fixes it at this point,
and bisection of that driver will fail if/when you walk into the
history of that driver. - Linus ]
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (96 commits)
soc: amlogic: meson-gx-pwrc-vpu: fix power-off when powered by bootloader
bus: add driver for the Technologic Systems NBUS
memory: omap-gpmc: Remove deprecated gpmc_update_nand_reg()
soc: qcom: remove unused label
soc: amlogic: gx pm domain: add PM and OF dependencies
drivers/firmware: psci_checker: Add missing destroy_timer_on_stack()
dt-bindings: power: add amlogic meson power domain bindings
soc: amlogic: add Meson GX VPU Domains driver
soc: qcom: Remote filesystem memory driver
dt-binding: soc: qcom: Add binding for rmtfs memory
of: reserved_mem: Accessor for acquiring reserved_mem
of/platform: Generalize /reserved-memory handling
soc: mediatek: pwrap: fix fatal compiler error
soc: mediatek: pwrap: fix compiler errors
arm64: mediatek: cleanup message for platform selection
soc: Allow test-building of MediaTek drivers
soc: mediatek: place Kconfig for all SoC drivers under menu
soc: mediatek: pwrap: add support for MT7622 SoC
soc: mediatek: pwrap: add common way for setup CS timing extenstion
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap
..
|
|
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
Add the reset controller dt-bindings exported from infracfg, pericfg,
hifsys and ethsys which could be found on MT7622 SoC. So that we can
reference them from within a device-tree file.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
There is no plan yet to do a v2 board. And even if we were to do it only
some IPs would actually change, so it be best to add suffixes at that
point, not now !
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
Pull clk updates from Stephen Boyd:
"The diff is dominated by the Allwinner A10/A20 SoCs getting converted
to the sunxi-ng framework. Otherwise, the heavy hitters are various
drivers for SoCs like AT91, Amlogic, Renesas, and Rockchip. There are
some other new clk drivers in here too but overall this is just a
bunch of clk drivers for various different pieces of hardware and a
collection of non-critical fixes for clk drivers.
New Drivers:
- Allwinner R40 SoCs
- Renesas R-Car Gen3 USB 2.0 clock selector PHY
- Atmel AT91 audio PLL
- Uniphier PXs3 SoCs
- ARC HSDK Board PLLs
- AXS10X Board PLLs
- STMicroelectronics STM32H743 SoCs
Removed Drivers:
- Non-compiling mb86s7x support
Updates:
- Allwinner A10/A20 SoCs converted to sunxi-ng framework
- Allwinner H3 CPU clk fixes
- Renesas R-Car D3 SoC
- Renesas V2H and M3-W modules
- Samsung Exynos5420/5422/5800 audio fixes
- Rockchip fractional clk approximation fixes
- Rockchip rk3126 SoC support within the rk3128 driver
- Amlogic gxbb CEC32 and sd_emmc clks
- Amlogic meson8b reset controller support
- IDT VersaClock 5P49V5925/5P49V6901 support
- Qualcomm MSM8996 SMMU clks
- Various 'const' applications for struct clk_ops
- si5351 PLL reset bugfix
- Uniphier audio on LD11/LD20 and ethernet support on LD11/LD20/Pro4/PXs2
- Assorted Tegra clk driver fixes"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (120 commits)
clk: si5351: fix PLL reset
ASoC: atmel-classd: remove aclk clock
ASoC: atmel-classd: remove aclk clock from DT binding
clk: at91: clk-generated: make gclk determine audio_pll rate
clk: at91: clk-generated: create function to find best_diff
clk: at91: add audio pll clock drivers
dt-bindings: clk: at91: add audio plls to the compatible list
clk: at91: clk-generated: remove useless divisor loop
clk: mb86s7x: Drop non-building driver
clk: ti: check for null return in strrchr to avoid null dereferencing
clk: Don't write error code into divider register
clk: uniphier: add video input subsystem clock
clk: uniphier: add audio system clock
clk: stm32h7: Add stm32h743 clock driver
clk: gate: expose clk_gate_ops::is_enabled
clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()
clk: uniphier: add PXs3 clock data
clk: hi6220: change watchdog clock source
clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808
clk: cs2000: Add cs2000_set_saved_rate
...
|
|
Pull ARM/arm64 Devicetree updates from Olof Johansson:
"As usual, device tree updates is the bulk of our material in this
merge window. This time around, 559 patches affecting both 32- and
64-bit platforms.
Changes are too many to list individually, but some of the larger
ones:
New platform/SoC support:
- Automotive:
+ Renesas R-Car D3 (R8A77995)
+ TI DT76x
+ MediaTek mt2712e
- Communication-oriented:
+ Qualcomm IPQ8074
+ Broadcom Stingray
+ Marvell Armada 8080
- Set top box:
+ Uniphier PXs3
Besides some vendor reference boards for the SoC above, there are also
several new boards/machines:
- TI AM335x Moxa UC-8100-ME-T open platform
- TI AM57xx Beaglebone X15 Rev C
- Microchip/Atmel sama5d27 SoM1 EK
- Broadcom Raspberry Pi Zero W
- Gemini-based D-Link DIR-685 router
- Freescale i.MX6:
+ Toradex Apalis module + Apalis and Ixora carrier boards
+ Engicam GEAM6UL Starter Kit
- Freescale i.MX53-based Beckhoff CX9020 Embedded PC
- Mediatek mt7623-based BananaPi R2
- Several Allwinner-based single-board computers:
+ Cubietruck plus
+ Bananapi M3, M2M and M64
+ NanoPi A64
+ A64-OLinuXino
+ Pine64
- Rockchip RK3328 Pine64/Rock64 board support
- Rockchip RK3399 boards:
+ RK3399 Sapphire module on Excavator carrier (RK3399 reference design)
+ Theobroma Systems RK3399-Q7 SoM
- ZTE ZX296718 PCBOX Board"
* tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (559 commits)
ARM: dts: at91: at91sam9g45: add AC97
arm64: dts: marvell: mcbin: enable more networking ports
arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 node
arm64: dts: marvell: add TX interrupts for PPv2.2
arm64: dts: uniphier: add PXs3 SoC support
ARM: dts: uniphier: add pinctrl groups of ethernet phy mode
ARM: dts: uniphier: fix size of sdctrl nodes
ARM: dts: uniphier: add AIDET nodes
arm64: dts: uniphier: fix size of sdctrl node
arm64: dts: uniphier: add AIDET nodes
Revert "ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2"
arm64: dts: uniphier: add reset controller node of analog amplifier
arm64: dts: marvell: add Device Tree files for Armada-8KP
arm64: dts: rockchip: add Haikou baseboard with RK3399-Q7 SoM
arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM
dt-bindings: add rk3399-q7 SoM
ARM: dts: rockchip: enable usb for rv1108-evb
ARM: dts: rockchip: add usb nodes for rv1108 SoCs
dt-bindings: update grf-binding for rv1108 SoCs
ARM: dts: aspeed-g4: fix AHB window size of the SMC controllers
...
|
|
Pull more Allwinner clock changes from Maxime Ripard:
* Conversion of the last two SoCs (A10, A20) to the sunxi-ng framework
* tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: Add sun4i/sun7i CCU driver
dt-bindings: List devicetree binding for the CCU of Allwinner A10
dt-bindings: List devicetree binding for the CCU of Allwinner A20
|
|
Introduce a clock controller driver for sun4i A10 and sun7i A20
series SoCs.
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
Pull Allwinner clock changes from Chen-Yu Tsai:
* Added support for fixed post-divider on divider and NKM-style clocks
* Added driver for R40 CCU
* Fix sunxi-ng/ccu-sunxi-r.h header file guard macro typo
* Make fractional clock modes really used and correctly configured
* Make H3 cpu clock rate change correctly to be used with cpufreq
* tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: support R40 SoC
dt-bindings: add compatible string for Allwinner R40 CCU
clk: sunxi-ng: nkm: add support for fixed post-divider
clk: sunxi-ng: div: Add support for fixed post-divider
dt-bindings: clock: sunxi-ccu: Add compatibles for sun5i CCU driver
clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
clk: sunxi-ng: Wait for lock when using fractional mode
clk: sunxi-ng: Make fractional helper less chatty
clk: sunxi-ng: multiplier: Fix fractional mode
clk: sunxi-ng: Fix fractional mode for N-M clocks
clk: sunxi-ng: Fix header guard of ccu-sun8i-r.h
|
|
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
|
|
The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset
lines. These are used for example to boot the secondary CPU cores.
This patch describes the reset controller which is embedded into the
clock controller on these SoCs.
A header file is provided which provides preprocessor macros for each
reset line (to make the .dts files easier to read).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
|
The HSDK v1 periphery IPs can be reset by accessing some registers
from the CGU block.
The list of available reset lines is documented in the DT bindings.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
Pull clk updates from Stephen Boyd:
"This time we've got one core change to introduce a bulk clk_get API,
some new clk drivers and updates for old ones. The diff is pretty
spread out across a handful of different SoC clk drivers for Broadcom,
TI, Qualcomm, Renesas, Rockchip, Samsung, and Allwinner, mostly due to
the introduction of new drivers.
Core:
- New clk bulk get APIs
- Clk divider APIs gained the ability to consider a different parent
than the current one
New Drivers:
- Renesas r8a779{0,1,2,4} CPG/MSSR
- TI Keystone SCI firmware controlled clks and OMAP4 clkctrl
- Qualcomm IPQ8074 SoCs
- Cortina Systems Gemini (SL3516/CS3516)
- Rockchip rk3128 SoCs
- Allwinner A83T clk control units
- Broadcom Stingray SoCs
- CPU clks for Mediatek MT8173/MT2701/MT7623 SoCs
Removed Drivers:
- Old non-DT version of the Realview clk driver
Updates:
- Renesas Kconfig/Makefile cleanups
- Amlogic CEC EE clk support
- Improved Armada 7K/8K cp110 clk support
- Rockchip clk id exposing, critical clk markings
- Samsung converted to clk_hw registration APIs
- Fixes for Samsung exynos5420 audio clks
- USB2 clks for Hisilicon hi3798cv200 SoC and video/camera clks for
hi3660"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (147 commits)
clk: gemini: Read status before using the value
clk: scpi: error when clock fails to register
clk: at91: Add sama5d2 suspend/resume
gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K
clk: keystone: TI_SCI_PROTOCOL is needed for clk driver
clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled EPLL
clk: uniphier: provide NAND controller clock rate
clk: hisilicon: add usb2 clocks for hi3798cv200 SoC
clk: Add Gemini SoC clock controller
clk: iproc: Remove __init marking on iproc_pll_clk_setup()
clk: bcm: Add clocks for Stingray SOC
dt-bindings: clk: Extend binding doc for Stingray SOC
clk: mediatek: export cpu multiplexer clock for MT8173 SoCs
clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs
clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work
clk: renesas: cpg-mssr: Use of_device_get_match_data() helper
clk: hi6220: add acpu clock
clk: zx296718: export I2S mux clocks
clk: imx7d: create clocks behind rawnand clock gate
clk: hi3660: Set PPLL2 to 2880M
...
|
|
This adds the DT binding macros used by the reset controller.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.
Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.
Also, the MMC2 module clock supports switching to a "new timing" mode.
This mode divides the clock output by half, and disables the CCU based
clock delays. The MMC controller must be configure to the same mode,
and then use its internal clock delays.
This driver does not support runtime switching of the timing modes.
Instead, the new timing mode is enforced at probe time. Consumers can
check which mode is active by trying to get the current phase delay
of the MMC2 phase clocks, which will return -ENOTSUPP if the new
timing mode is active.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
Allwinner "Display Engine 2.0" contains some clock controls in it.
In order to add them as clock drivers, we need a device tree binding.
Add the binding here.
Also add the device tree binding headers.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
There are several changes in reset manager offsets from Arria10 to
Stratix10. This patch is based on one from Arria10 and adds offset
updates for Stratix10
Signed-off-by: Richard Gong <richard.gong@intel.com>
|
|
This adds the DT binding macros used by the reset controller.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
Pull clk updates from Stephen Boyd:
"Sort of on the quieter side this time, which is probably due more to
me not catching up as quickly on patch review than anything else.
Overall it seems normal though, a few small changes to the core,
mostly small non-critical fixes here and there as well as driver
updates for new and existing hardware support.
The biggest things are the TI clk driver rework to lay the groundwork
for clkctrl support in the next merge window and the AmLogic
audio/graphics clk support.
Core:
- clk_possible_parents debugfs file so we know which parents a clk
could possibly have
- Fix to make clk rate change notifiers stop on the first failure
instead of continuing
New Drivers:
- Mediatek MT6797 SoCs
- hi655x PMIC clks
- AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
- Allwinner H5 SoCs and PRCM hardware
Updates:
- Nvidia Tegra T210 cleanups and non-critical fixes
- TI OMAP cleanups in preparation for clkctrl support
- trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
- ZTE zx296718 SoC VGA clks
- Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
- IDT VersaClock 5P49V5935 support
- Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3
support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (151 commits)
clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL
clk: ti: divider: try to fix ti_clk_register_divider
clk: mvebu: Use kcalloc() in two functions
clk: mvebu: Use kcalloc() in of_cpu_clk_setup()
clk: nomadik: Delete error messages for a failed memory allocation in two functions
clk: nomadik: Use seq_puts() in nomadik_src_clk_show()
clk: Improve a size determination in two functions
clk: Replace four seq_printf() calls by seq_putc()
clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe()
clk: si5351: Use devm_kcalloc() in si5351_i2c_probe()
clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics()
reset: mediatek: Add MT2701 ethsys reset controller include file
clk: mediatek: add mt2701 ethernet reset
clk: hi6220: Add the hi655x's pmic clock
clk: ti: fix building without legacy omap3
clk: ti: fix linker error with !SOC_OMAP4
clk: hi3620: Fix a typo in one variable name
clk: hi3620: Delete error messages for a failed memory allocation in two functions
clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()
clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init()
...
|
|
Add the missing reset bits of the ethsys core to the mt2701-reset include
file, so that we can reference them from within a devicetree file.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
Pull Allwinner clock patches for 4.12 from Maxime Ripard:
Support for the new H5 SoC and the PRCM block found in a number of SoCs as
well, plus the usual chunk of fixes and minor enhancements.
* tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: Display index when clock registration fails
clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor
clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks
clk: sunxi-ng: mult: Support PLL lock detection
clk: sunxi-ng: add support for PRCM CCUs
dt-bindings: update device tree binding for Allwinner PRCM CCUs
clk: sunxi-ng: sun5i: Fix mux width for csi clock
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs
clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
clk: sunxi-ng: gate: Support common pre-dividers
|
|
SoCs after A31 has a clock controller module in the PRCM part.
Support the clock controller module on H3/5 and A64 now.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
Tegra210 has 2 special resets which don't follow the normal pattern:
DVCO and ADSP. Add them in this patch.
Changelog:
v2: add DT bindings file
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
The Arria10 System Resource Chip reset controller handles the
Arria10 peripheral PHYs. This patch adds the offsets for
these PHYs.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
Add reset controller driver exposing various reset faculties,
implemented by System Reset Controller IP block.
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
Allwinner H5 is a SoC that features a design which keeps the peripheral
compatible with H3, so that it have also a CCU like the one on H3 --
only one bus gate/reset is added, and the mmc sample/output phases are
removed because of MMC controller update.
Add its support in our existing H3 CCU driver.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
With the A80 SoC, Allwinner grouped and moved some subsystem specific
clock controls to a separate address space, and possibly separate
hardware block.
One such subsystem is the display engine. The main clock control unit
now only has 1 set of bus gate, dram gate, module clock, and reset
control for the entire display subsystem. These feed into a secondary
clock control unit, which has controls for each individual module
of the display pipeline. This block is not documented in the user
manual. Allwinner's kernel was used as the reference.
Add support for the display engine clock controls found on the A80.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
Add support for the USB clock controls found on the A80.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
Add support for the main clock unit found in the A80. Some clocks were
not documented in the released user manual, but were found in the
official kernel from Allwinner. These include controls for the I2S,
SPDIF, SATA, and eDP blocks.
Note that on the A80, some subsystems have separate clock controllers
downstream of the main clock unit. These include the MMC, USB, and
display engine subsystems.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
The Allwinner A10s, A13, R8 and NextThing GR8 are all based on the same
silicon, and all share the same clocks.
However, they're not packaged in the same way, and therefore not all the
controllers are actually available on all these SoCs.
Introduce a clock controller driver for all these SoCs with different
compatibles to take that into account.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks
about CSI, are different, which makes it to need a new CCU driver.
Add such a new driver for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
Pull ARM SoC driver updates from Arnd Bergmann:
"Driver updates for ARM SoCs, including a couple of newly added
drivers:
- A new driver for the power management controller on TI Keystone
- Support for the prerelease "SCPI" firmware protocol that ended up
being shipped by Amlogic in their GXBB SoC.
- A soc_device can now be matched using a glob from inside the
kernel, when another driver wants to know the specific chip it is
running on and cannot find out from DT, firmware or hardware.
- Renesas SoCs now support identification through the soc_device
interface, both in user space and kernel.
- Renesas r8a7743 and r8a7745 gain support for their system
controller
- A new checking module for the ARM "PSCI" (not to be confused with
"SCPI" mentioned above) firmware interface.
- A new driver for the Tegra GMI memory interface
- Support for the Tegra firmware interfaces with their power
management controllers
As usual, the updates for the reset controller framework are merged
here, as they tend to touch multiple SoCs as well, including a new
driver for the Oxford (now Broadcom) OX820 chip and the Tegra bpmp
interface.
The existing drivers for Atmel, Qualcomm, NVIDIA, TI Davinci, and
Rockchips SoCs see some further updates"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (76 commits)
misc: sram: remove useless #ifdef
drivers: psci: Allow PSCI node to be disabled
drivers: psci: PSCI checker module
soc: renesas: Identify SoC and register with the SoC bus
firmware: qcom: scm: Return PTR_ERR when devm_clk_get fails
firmware: qcom: scm: Remove core, iface and bus clocks dependency
dt-bindings: firmware: scm: Add MSM8996 DT bindings
memory: da8xx-ddrctl: drop the call to of_flat_dt_get_machine_name()
bus: da8xx-mstpri: drop the call to of_flat_dt_get_machine_name()
ARM: shmobile: Document DT bindings for Product Register
soc: renesas: rcar-sysc: add R8A7745 support
reset: Add Tegra BPMP reset driver
dt-bindings: firmware: Allow child nodes inside the Tegra BPMP
dt-bindings: Add power domains to Tegra BPMP firmware
firmware: tegra: Add BPMP support
firmware: tegra: Add IVC library
dt-bindings: firmware: Add bindings for Tegra BPMP
mailbox: tegra-hsp: Use after free in tegra_hsp_remove_doorbells()
mailbox: Add Tegra HSP driver
firmware: arm_scpi: add support for pre-v1.0 SCPI compatible
...
|
|
firmware: Add Tegra IVC and BPMP support
IVC is an inter-processor communication protocol that uses shared memory
to exchange data between processors. The BPMP driver makes use of this
to communicate with the Boot and Power Management Processor (BPMP) and
uses an additional hardware synchronization primitive from the HSP block
to signal availability of new data (doorbell).
Firmware running on the BPMP implements a number of services such as the
control of clocks and resets within the system, or the ability to ungate
or gate power partitions.
* tag 'tegra-for-4.10-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: firmware: Allow child nodes inside the Tegra BPMP
dt-bindings: Add power domains to Tegra BPMP firmware
firmware: tegra: Add BPMP support
firmware: tegra: Add IVC library
dt-bindings: firmware: Add bindings for Tegra BPMP
Signed-off-by: Olof Johansson <olof@lixom.net>
|
|
The Boot and Power Management Processor (BPMP) is a co-processor found
in Tegra SoCs. It is designed to handle the early stages of the boot
process as well as to offload power management tasks (such as clocks,
resets, powergates, ...).
The binding document defines the resources that are used by the BPMP
firmware, which implements the interprocessor communication (IPC)
between the CPU and the BPMP.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
Add the A64 CCU clocks set.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
Add DT include file for Oxford Semiconductor OX810SE and OX820 reset
controller support.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
Pull Allwinner clock driver changes from Maxime Ripard:
Four more SoCs converted to the new clock framework (A31, A31s, A23 and
A33).
* tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
clk: sunxi-ng: Add hardware dependency
clk: sunxi-ng: Add A23 CCU
clk: sunxi-ng: Add A33 CCU support
clk: sunxi-ng: Add N-class clocks support
clk: sunxi-ng: mux: Add mux table macro
clk: sunxi-ng: div: Allow to set a maximum
clk: sunxi-ng: div: Add kerneldoc for the _ccu_div structure
clk: sunxi-ng: div: Add mux table macros
clk: sunxi-ng: Add A31/A31s clocks
clk: sunxi-ng: mux: Add clk notifier functions
clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents
clk: sunxi-ng: mux: Add support for mux tables
clk: sunxi-ng: mux: Rename mux macro to be consistent
clk: sunxi-ng: nkm: Add mux to support multiple parents
clk: sunxi-ng: mux: Increase fixed pre-divider div size
|
Jerome Brunet
Sibi Sankar
Stephen Boyd
Sean Wang
Yixun Lan
Icenowy Zheng
Linus Torvalds
Gabriel Fernandez
Mikko Perttunen
Greg Kroah-Hartman
Vineet Gupta
Stephen Boyd
Priit Laes
Martin Blumenstingl
Eugeniy Paltsev
Linus Walleij
Chen-Yu Tsai
Richard Gong
John Crispin
Icenowy Zheng
Peter De Schrijver
Thor Thayer
Andrey Smirnov
Maxime Ripard
Olof Johansson
Joseph Lo
Neil Armstrong