aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux/clk-provider.h (follow)
AgeCommit message (Collapse)AuthorFilesLines
2015-10-26clk: Add clk_hw_is_enabled() for use by clk providersJoachim Eastwood1-0/+1
Add clk_hw_is_enabled() to the provider APIs so clk providers can use a struct clk_hw instead of a struct clk to check if a clk is enabled or not. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-26clk: Add stubs for of_clk_*() APIs when CONFIG_OF=nStephen Boyd1-0/+9
Compiling the versatile clock driver with COMPILE_TEST=y and CONFIG_OF=n leads to the following error: drivers/clk/versatile/clk-sp810.c: In function 'clk_sp810_of_setup': drivers/clk/versatile/clk-sp810.c:103:6: error: implicit declaration of function 'of_clk_parent_fill' [-Werror=implicit-function-declaration] Silence it by providing stubs APIs for of_clk_parent_fill(). Throw in a stub for of_clk_get_parent_count() too because we're in the area. Reported-by: kbuild test robot <fengguang.wu@intel.com> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-23clk: Remove clk_{register,unregister}_multiplier()Stephen Boyd1-7/+0
These APIs aren't used, so remove them. This can be reverted if we get a user at some point. Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com> Suggested-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21Merge tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-nextStephen Boyd1-0/+42
Pull Allwinner clock additions for 4.4 from Maxime Ripard: - Support for the Audio PLL and child clocks - Support for the A33 AHB gates - New clk-multiplier generic driver * tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi: mod1 clock support clk: sunxi: codec clock support clk: sunxi: pll2: Add A13 support clk: sunxi: Add a driver for the PLL2 clk: Add a basic multiplier clock clk: sunxi: Add A33 gates support
2015-10-21clk: Add a basic multiplier clockMaxime Ripard1-0/+42
Some clocks are using a multiplier component, however, unlike their mux, gate or divider counterpart, these factors don't have a basic clock implementation. This leads to code duplication across platforms that want to use that kind of clocks, and the impossibility to use the composite clocks with such a clock without defining your own rate operations. Create such a driver in order to remove these issues, and hopefully factor the implementations, reducing code size across platforms and consolidating the various implementations. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2015-10-16clk: Make clk input parameter of __clk_get_name() constGeert Uytterhoeven1-1/+1
When calling __clk_get_name() on a const clock: warning: passing argument 1 of '__clk_get_name' discards 'const' qualifier from pointer target type include/linux/clk-provider.h:613:13: note: expected 'struct clk *' but argument is of type 'const struct clk *' __clk_get_name() does not modify the passed clock, hence make it const. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-02clk: fractional-divider: keep mwidth and nwidth internallyAndy Shevchenko1-1/+2
The patch adds mwidth and nwidth fields to the struct clk_fractional_divider for further usage. While here, use GENMASK() instead of open coding this functionality. Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: Constify clk_hw argument to provider APIsStephen Boyd1-7/+7
We don't modify the clk_hw argument in these functions, so it's safe to mark it as const. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: Remove unused provider APIsStephen Boyd1-6/+0
Remove these APIs now that we've converted all users to the replacement struct clk_hw based versions. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: Add clk_hw_*() APIs for use by clk providersStephen Boyd1-0/+9
clk providers shouldn't need to use the consumer APIs (clk.h). Add provider APIs to replace the __clk_*() APIs that take a struct clk_hw as their first argument instead of a struct clk. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28clk: gpio: Mark parent_names array constStephen Boyd1-1/+1
Let's encourage const arrays of parent names like other basic clock types. Cc: Sergej Sawazki <ce3a@gmx.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28clk: allow a clk divider with max divisor when zeroJim Quinlan1-0/+4
This commit allows certain Broadcom STB clock dividers to be used with clk-divider.c. It allows for a clock whose field value is the equal to the divisor, execpt when the field value is zero, in which case the divisor is 2^width. For example, consider a divisor clock with a two bit field: value divisor 0 4 1 1 2 2 3 3 Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd1-1/+1
* cleanup-clk-h-includes: (62 commits) clk: Remove clk.h from clk-provider.h clk: h8300: Remove clk.h and clkdev.h includes clk: at91: Include clk.h and slab.h clk: ti: Switch clk-provider.h include to clk.h clk: pistachio: Include clk.h clk: ingenic: Include clk.h clk: si570: Include clk.h clk: moxart: Include clk.h clk: cdce925: Include clk.h clk: Include clk.h in clk.c clk: zynq: Include clk.h clk: ti: Include clk.h clk: sunxi: Include clk.h and remove unused clkdev.h includes clk: st: Include clk.h clk: qcom: Include clk.h clk: highbank: Include clk.h clk: bcm: Include clk.h clk: versatile: Remove clk.h and clkdev.h includes clk: ux500: Remove clk.h and clkdev.h includes clk: tegra: Properly include clk.h ...
2015-07-28clk: Allow providers to configure min/max ratesStephen Boyd1-0/+2
clk providers are using the consumer APIs to set min/max rates on the clock they're providing. To encourage clk providers to move away from the consumer APIs, add a provider API to set the min/max rate of a clock. The assumption is that this is done before the clock can be requested via clk_get() and that the clock rate is already within the boundaries of the min/max that's configured. Tested-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28Merge branch 'clk-determine-rate-struct' into clk-nextStephen Boyd1-20/+29
* clk-determine-rate-struct: clk: fix some determine_rate implementations clk: change clk_ops' ->determine_rate() prototype
2015-07-27clk: change clk_ops' ->determine_rate() prototypeBoris Brezillon1-20/+29
Clock rates are stored in an unsigned long field, but ->determine_rate() (which returns a rounded rate from a requested one) returns a long value (errors are reported using negative error codes), which can lead to long overflow if the clock rate exceed 2Ghz. Change ->determine_rate() prototype to return 0 or an error code, and pass a pointer to a clk_rate_request structure containing the expected target rate and the rate constraints imposed by clk users. The clk_rate_request structure might be extended in the future to contain other kind of constraints like the rounding policy, the maximum clock inaccuracy or other things that are not yet supported by the CCF (power consumption constraints ?). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Jonathan Corbet <corbet@lwn.net> CC: Tony Lindgren <tony@atomide.com> CC: Ralf Baechle <ralf@linux-mips.org> CC: "Emilio López" <emilio@elopez.com.ar> CC: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Tero Kristo <t-kristo@ti.com> CC: Peter De Schrijver <pdeschrijver@nvidia.com> CC: Prashant Gaikwad <pgaikwad@nvidia.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Thierry Reding <thierry.reding@gmail.com> CC: Alexandre Courbot <gnurou@gmail.com> CC: linux-doc@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-omap@vger.kernel.org CC: linux-mips@linux-mips.org CC: linux-tegra@vger.kernel.org [sboyd@codeaurora.org: Fix parent dereference problem in __clk_determine_rate()] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> [sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate clocks without parents or a rate determining op] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20clk: Remove clk.h from clk-provider.hStephen Boyd1-1/+1
Remove clk.h from clk-provider.h so that we can clearly split clk providers from clk consumers. This will allow us to quickly detect when clock providers are using the consumer APIs by looking at the includes. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06clk: add gpio controlled clock multiplexerSergej Sawazki1-0/+17
Add a common clock driver for basic gpio controlled clock multiplexers. This driver can be used for devices like 5V41068A or 831721I from IDT or for discrete multiplexer circuits. The 'select' pin selects one of two parent clocks. Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by: Sergej Sawazki <ce3a@gmx.de> [sboyd@codeaurora.org: Fix error paths to free memory and do it in the correct order] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-20Merge tag 'tegra-for-4.2-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-nextMichael Turquette1-0/+1
clk: tegra: Changes for v4.2-rc1 This contains the EMC clock driver that's been exhaustively reviewed and tested. It also includes a change to the clock core that allows a clock provider to perform low-level reparenting of clocks. This is required by the EMC clock driver because the reparenting needs to be done at a very specific point in time during the EMC frequency switch.
2015-06-20Merge branch 'clk-exynos-cpu-clk' into clk-nextMichael Turquette1-0/+1
Folded into this merge commit is a build error fix: s/clk/core in clk_change_rate due to the new struct clk_core
2015-06-20clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock supportBartlomiej Zolnierkiewicz1-0/+1
This flag is needed to fix the issue with wrong dividers being setup by Common Clock Framework when using the new Exynos cpu clock support. The issue happens because clk_core_set_rate_nolock() calls clk_calc_new_rates(clk, rate) before both pre/post clock notifiers have a chance to run. In case of Exynos cpu clock support pre/post clock notifiers are registered for mout_apll clock which is a parent of armclk cpu clock and dividers are modified in both pre and post clock notifier. This results in wrong dividers values being later programmed by clk_change_rate(top). To workaround the problem CLK_RECALC_NEW_RATES flag is added and it is set for mout_apll clock later so the correct divider values are re-calculated after both pre and post clock notifiers had run. For example when using "performance" governor on Exynos4210 Origen board the cpufreq-dt driver requests to change the frequency from 1000MHz to 1200MHz and after the change state of the relevant clocks is following: Without use of CLK_GET_RATE_NOCACHE flag: fout_apll rate: 1200000000 fout_apll_div_2 rate: 600000000 mout_clkout_cpu rate: 600000000 div_clkout_cpu rate: 600000000 clkout_cpu rate: 600000000 mout_apll rate: 1200000000 armclk rate: 1200000000 mout_hpm rate: 1200000000 div_copy rate: 300000000 div_hpm rate: 300000000 mout_core rate: 1200000000 div_core rate: 1200000000 div_core2 rate: 1200000000 arm_clk_div_2 rate: 600000000 div_corem0 rate: 300000000 div_corem1 rate: 150000000 div_periph rate: 300000000 div_atb rate: 300000000 div_pclk_dbg rate: 150000000 sclk_apll rate: 1200000000 sclk_apll_div_2 rate: 600000000 With use of CLK_GET_RATE_NOCACHE flag: fout_apll rate: 1200000000 fout_apll_div_2 rate: 600000000 mout_clkout_cpu rate: 600000000 div_clkout_cpu rate: 600000000 clkout_cpu rate: 600000000 mout_apll rate: 1200000000 armclk rate: 1200000000 mout_hpm rate: 1200000000 div_copy rate: 200000000 div_hpm rate: 200000000 mout_core rate: 1200000000 div_core rate: 1200000000 div_core2 rate: 1200000000 arm_clk_div_2 rate: 600000000 div_corem0 rate: 300000000 div_corem1 rate: 150000000 div_periph rate: 300000000 div_atb rate: 240000000 div_pclk_dbg rate: 120000000 sclk_apll rate: 150000000 sclk_apll_div_2 rate: 75000000 Without this change cpufreq-dt driver showed ~10 mA larger energy consumption when compared to cpufreq-exynos one when "performance" cpufreq governor was used on Exynos4210 SoC based Origen board. This issue was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in the original Exynos cpu clock patchset (in "[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update clock flags" patch) but usage of these flags is not sufficient to fix the issue observed. Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-06-10clk: fixed: Add comment to clk_fixed_set_rateDaniel Thompson1-1/+1
Currently it is not made explicit why clk_fixed_set_rate() can ignore its arguments and unconditionally return success. Add a comment to explain this. We also mark the clk_ops table const since it should never be modified at runtime. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-05clk: of: helper for filling parent clock array and return num of parentsDinh Nguyen1-0/+2
Sprinkled all through the platform clock drivers are code like this to fill the clock parent array: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); The of_clk_parent_fill() will do the same as the code above, and while at it, return the number of parents as well since the logic of the function is to the walk the clock node to look for the parent. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> [sboyd@codeaurora.org: Fixed kernel-doc] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-13clk: Expose clk_hw_reparent() to providersTomeu Vizoso1-0/+1
To be used by clock implementations for switching to a new parent during rate change. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-05-05clk: make strings in parent name arrays constSascha Hauer1-4/+6
The clk functions and structs declare the parent_name arrays as 'const char **parent_names' which means the parent name strings are const, but the array itself is not. Use 'const char * const * parent_names' instead which also makes the array const. This allows us to put the parent_name arrays into the __initconst section. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> [sboyd@codeaurora.org: Squelch 80-character checkpatch warnings] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-10clk: clk-gpio-gate: Fix active lowMartin Fuzzey1-1/+1
The active low flag in the DT cell is currently ignored. This occurs because of_get_named_gpio_flags() does not apply the flags to the underlying struct gpio_desc so the test in clk_register_gpio_gate() was bogus. Note that this patch changes the internal kernel API for clk_register_gpio_gate() but there are currently no other users. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Acked-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-18clk: Add __clk_hw_set_clk helper functionJavier Martinez Canillas1-0/+6
After the clk API change to return a per-user clock instance, both the struct clk_core and struct clk pointers from the hw clock needs to be assigned to clock that share the same state. In the future the struct clk_core will be removed and this is going to change again so to avoid having to change the assignments twice in all the drivers, add a helper function to have an indirection level. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-02clk: Add rate constraints to clocksTomeu Vizoso1-3/+14
Adds a way for clock consumers to set maximum and minimum rates. This can be used for thermal drivers to set minimum rates, or by misc. drivers to set maximum rates to assure a minimum performance level. Changes the signature of the determine_rate callback by adding the parameters min_rate and max_rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [sboyd@codeaurora.org: set req_rate in __clk_init] Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate migrated clk-private.h changes to clk.c]
2015-02-02clk: Make clk API return per-user struct clk instancesTomeu Vizoso1-5/+7
Moves clock state to struct clk_core, but takes care to change as little API as possible. struct clk_hw still has a pointer to a struct clk, which is the implementation's per-user clk instance, for backwards compatibility. The struct clk that clk_get_parent() returns isn't owned by the caller, but by the clock implementation, so the former shouldn't call clk_put() on it. Because some boards in mach-omap2 still register clocks statically, their clock registration had to be updated to take into account that the clock information is stored in struct clk_core now. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: adapted clk_has_parent to struct clk_core applied OMAP3+ DPLL fix from Tero & Tony]
2015-01-27clk: divider: Make generic for usage elsewhereStephen Boyd1-0/+11
Some devices don't use mmio to interact with dividers. Split out the logic from the register read/write parts so that we can reuse the division logic elsewhere. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27clk: Add __clk_mux_determine_rate_closestStephen Boyd1-1/+7
Some clock drivers want to find the closest rate on the input of a mux instead of a rate that's less than or equal to the desired rate. Add a generic mux function to support this. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-17clk: Add clk_unregister_{divider, gate, mux} to close memory leakKrzysztof Kozlowski1-0/+4
The common clk_register_{divider,gate,mux} functions allocated memory for internal data which wasn't freed anywhere. Drivers using these helpers could only unregister clocks but the memory would still leak. Add corresponding unregister functions which will release all resources. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-03clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso1-2/+2
This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-03clk: change clk_debugfs_add_file to take a struct clk_hwTomeu Vizoso1-1/+1
Instead of struct clk, as this should be only used by providers. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-03clk: Don't expose __clk_get_accuracyTomeu Vizoso1-1/+0
As it's only used internally, in drivers/clk/clk.c. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-03clk: Remove unused function __clk_get_prepare_countTomeu Vizoso1-1/+0
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17clk-divider: Fix READ_ONLY when divider > 1James Hogan1-1/+0
Commit 79c6ab509558 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the recalc_rate() and round_rate() clock callbacks to be omitted. However using this flag has the unfortunate side effect of causing the clock recalculation code when a clock rate change is attempted to always treat it as a pass-through clock, i.e. with a fixed divide of 1, which may not be the case. Child clock rates are then recalculated using the wrong parent rate. Therefore instead of dropping the recalc_rate() and round_rate() callbacks, alter clk_divider_bestdiv() to always report the current divider as the best divider so that it is never altered. For me the read only clock was the system clock, which divided the PLL rate by 2, from which both the UART and the SPI clocks were divided. Initial setting of the UART rate set it correctly, but when the SPI clock was set, the other child clocks were miscalculated. The UART clock was recalculated using the PLL rate as the parent rate, resulting in a UART new_rate of double what it should be, and a UART which spewed forth garbage when the rate changes were propagated. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Max Schwarz <max.schwarz@online.de> Cc: <stable@vger.kernel.org> # v3.16+ Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-09-27Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-nextMike Turquette1-0/+11
Allwinner Clocks Additions for 3.18 The most important part of this serie is the addition of the phase API to handle the MMC clocks in the Allwinner SoCs. Apart from that, the A23 gained a new mbus driver, and there's a fix for a incorrect divider table on the APB0 clock.
2014-09-27clk: Add a function to retrieve phaseMaxime Ripard1-0/+5
The current phase API doesn't look into the actual hardware to get the phase value, but will rather get it from a variable only set by the set_phase function. This will cause issue when the client driver will never call the set_phase function, where we can end up having a reported phase that will not match what the hardware has been programmed to by the bootloader or what phase is programmed out of reset. Add a new get_phase function for the drivers to implement so that we can get this value. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27clk: Include of.h in clock-provider.hMaxime Ripard1-0/+1
CLK_OF_DECLARE relies on OF_DECLARE_1 that is defined in of.h. Fixes build errors when one use CLK_OF_DECLARE but doesn't include of.h Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27clk: introduce clk_set_phase function & callbackMike Turquette1-0/+5
A common operation for a clock signal generator is to shift the phase of that signal. This patch introduces a new function to the clk.h API to dynamically adjust the phase of a clock signal. Additionally this patch introduces support for the new function in the common clock framework via the .set_phase call back in struct clk_ops. Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-26clk: add gpio gated clockJyri Sarha1-0/+22
The added gpio-gate-clock is a basic clock that can be enabled and disabled trough a gpio output. The DT binding document for the clock is also added. For EPROBE_DEFER handling the registering of the clock has to be delayed until of_clk_get() call time. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-02clk: define and export clk_debugs_add_filePeter De Schrijver1-0/+5
Define and export a new function clk_debugs_add_file which adds a file to a existing clock's debugfs directory. This can be used by clock providers to add debugfs entries which are not related to a specific clock type. Examples include the ability to measure the rate of a clock. It can also be used by modules to create new debugfs entries. This is useful if you want to expose features for testing which can potentially cause system instability such as allowing to change a clock's rate from userspace. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-06-07Merge tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux into nextLinus Torvalds1-57/+70
Pull clock framework updates from Mike Turquette: "The clock framework changes for 3.16 are pretty typical: mostly clock driver additions and fixes. There are additions to the clock core code for some of the basic types (e.g. the common divider type has some fixes and featured added to it). One minor annoyance is a last-minute dependency that wasn't handled quite right. Commit ba0fae3b06a6 ("clk: berlin: add core clock driver for BG2/BG2CD") in this pull request depends on include/dt-bindings/clock/berlin2.h, which is already in your tree via the arm-soc pull request. Building for the berlin platform will break when the clk tree is built on it's own, but merged into your master branch everything should be fine" * tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux: (75 commits) mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs clk: export __clk_round_rate for providers clk: versatile: free icst on error return clk: qcom: Return error pointers for unimplemented clocks clk: qcom: Support msm8974pro global clock control hardware clk: qcom: Properly support display clocks on msm8974 clk: qcom: Support display RCG clocks clk: qcom: Return highest rate when round_rate() exceeds plan clk: qcom: Fix mmcc-8974's PLL configurations clk: qcom: Fix clk_rcg2_is_enabled() check clk: berlin: add core clock driver for BG2Q clk: berlin: add core clock driver for BG2/BG2CD clk: berlin: add driver for BG2x complex divider cells clk: berlin: add driver for BG2x simple PLLs clk: berlin: add driver for BG2x audio/video PLL clk: st: Terminate of match table clk/exynos4: Fix compilation warning ARM: shmobile: r8a7779: Add clock index macros for DT sources clk: divider: Fix overflow in clk_divider_bestdiv clk: u300: Terminate of match table ...
2014-06-04Merge tag 'devicetree-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into nextLinus Torvalds1-4/+1
Pull DeviceTree updates from Rob Herring: - Another round of clean-up of FDT related code in architecture code. This removes knowledge of internal FDT details from most architectures except powerpc. - Conversion of kernel's custom FDT parsing code to use libfdt. - DT based initialization for generic serial earlycon. The introduction of generic serial earlycon support went in through the tty tree. - Improve the platform device naming for DT probed devices to ensure unique naming and use parent names instead of a global index. - Fix a race condition in of_update_property. - Unify the various linker section OF match tables and fix several function prototype errors. - Update platform_get_irq_byname to work in deferred probe cases. - 2 binding doc updates * tag 'devicetree-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (58 commits) of: handle NULL node in next_child iterators of/irq: provide more wrappers for !CONFIG_OF devicetree: bindings: Document micrel vendor prefix dt: bindings: dwc2: fix required value for the phy-names property of_pci_irq: kill useless variable in of_irq_parse_pci() of/irq: do irq resolution in platform_get_irq_byname() of: Add a testcase for of_find_node_by_path() of: Make of_find_node_by_path() handle /aliases of: Create unlocked version of for_each_child_of_node() lib: add glibc style strchrnul() variant of: Handle memory@0 node on PPC32 only pci/of: Remove dead code of: fix race between search and remove in of_update_property() of: Use NULL for pointers of: Stop naming platform_device using dcr address of: Ensure unique names without sacrificing determinism tty/serial: pl011: add DT based earlycon support of/fdt: add FDT serial scanning for earlycon of/fdt: add FDT address translation support serial: earlycon: add DT support ...
2014-05-23clk: divider: add CLK_DIVIDER_READ_ONLY flagHeiko Stuebner1-0/+4
From: Heiko Stuebner <heiko@sntech.de> Similar to muxes which already have a read-only flag there sometimes exist dividers which should not be changed by the clock framework but whose value still should be readable. Therefore add a READ_ONLY flag similar to the mux-one to clk-divider Signed-off-by: Heiko Stuebner <heiko@sntech.de> [changed flag bit to BIT(5) as suggested by Tomasz Figa] Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Max Schwarz <max.schwarz@online.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-20of: consolidate linker section OF match table declarationsRob Herring1-4/+1
We now have several OF match tables using linker sections that are nearly the same definition. The only variation is the callback function prototype. Create a common define for creating linker section OF match table entries which each table declaration can use. Acked-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org>
2014-05-20clk: new basic clk type for fractional dividerHeikki Krogerus1-0/+31
Fractional divider clocks are fairly common. This adds basic type for them. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2014-05-12clk: Improve clk_ops documentationGeert Uytterhoeven1-19/+25
General: - Add parameter names to .round_rate() and .set_rate(). Documentation/clk.txt: - Add missing parameter for .set_rate(), - Add missing .debug_init(). include/linux/clk-provider.h: - Add parent rate documentation for .round_rate(), - Reorder documentation to match implementation order, - Add missing documentation for .init(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-12clk: Fixup spacing in commentsGeert Uytterhoeven1-44/+44
- Remove spaces in front of TABs, - Correct indentation for some CLK_* flag descriptions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.