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2015-11-03drm/nouveau/gr: document mp error 0x10Ilia Mirkin1-0/+1
NVIDIA provided the documentation for mp error 0x10, INVALID_ADDR_SPACE, which apparently happens when trying to use an atomic operation on local or shared memory (instead of global memory). Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau: fix memory leakSudip Mukherjee1-1/+3
If pm_runtime_get_sync() we were going to "out" but we missed freeing vma. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau: remove unused functionSudip Mukherjee2-15/+0
coverity.com reported that memset was using a buffer of size 0, on checking the code it turned out that the function was not being used. So remove it. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pmu/gk107: enable PGOB codepathsBen Skeggs1-1/+1
Reported to be needed as per fdo#70354 comment #61. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pmu/gk104: check fuse to determine presence of PGOBBen Skeggs1-0/+4
Not 100% confirmed, but seems to match from the few boards I've looked at so far. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci: prepare for chipset-specific initialisation tasksBen Skeggs2-0/+4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci/nv46: attempt to fix msi, and re-enable by defaultBen Skeggs6-12/+12
Was not able to obtain a trace of NVRM due to kernel version annoyances, however, experimentally confirmed that the WAR we use on NV50/G8x boards works here too. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci/g94: split implementation from nv40Ben Skeggs6-26/+67
An upcoming patch will implement functionality that we don't use on any NV40 chipset. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci/g84: split implementation from nv50Ben Skeggs6-5/+49
An upcoming patch will implement functionality that we don't use on the original NV50. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ibus/gf100: increase wait timeout to avoid read faultsSamuel Pitoiset6-4/+77
Increase clock timeout of some unknown engines in order to avoid failure at high gpcclk rate. This fixes IBUS read faults on my GF119 when reclocking is manually enabled. Note that memory reclocking is completely broken and NvMemExec has to be disabled to allow core clock reclocking only. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/gm204/6: add voltage control using the new gk104 volt classMartin Peres1-0/+2
I got confirmation that we can read and change the voltage with the same code. The divider is also computed correctly on the gm204 we got our hands on. Thanks to Yoshimo on IRC for executing the tests on his gm204! Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/gm107: add voltage control using the new gk104 volt classMartin Peres1-0/+1
Let's ignore the other desktop Maxwells until I get my hands on one and confirm that we still can change the voltage. Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-03drm/nouveau/volt/gk104: add support for pwm and gpio modesMartin Peres6-7/+133
Most Keplers actually use the GPIO-based voltage management instead of the new PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles the case where no GPIOs exist. All the Maxwells seem to use the PWM method though. v2: - Do not forget to commit the PWM configuration change! Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-03drm/nouveau/volt: add support for non-vid-based voltage controllersMartin Peres2-1/+12
This patch is not ideal but it definitely beats a rewrite of the current interface and is very self-contained. Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/bios/volt: add support for pwm-based volt managementMartin Peres2-3/+29
Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ttm: set the DMA mask for platform devicesAlexandre Courbot1-6/+19
So far the DMA mask was not set for platform devices, which limited them to a 32-bit physical space. Allow dma_set_mask() to be called for non-PCI devices, and also take the IOMMU bit into account since it could restrict the physically addressable space. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ttm: convert to DMA APIAlexandre Courbot1-7/+5
The pci_dma_* functions are now superseeded in the kernel by the DMA API. Make the conversion to this more generic API. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/instmem/gk20a: make use of the IOMMU bitAlexandre Courbot1-4/+6
Use the IOMMU bit specified in platform data instead of hardcoding it to the bit used by current Tegra GPUs. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/platform: allow to specify the IOMMU bitAlexandre Courbot6-10/+46
Current Tegra code taking advantage of the IOMMU assumes a hardcoded value for the IOMMU bit. Make it a platform property instead for flexibility. v2 (Ben Skeggs): remove nvkm dependence on drm structures Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/instmem/gk20a: use direct CPU accessAlexandre Courbot1-97/+264
The Great Nouveau Refactoring Take II brought us a lot of goodness, including acquire/release methods that are called before and after an instobj is modified. These functions can be used as synchronization points to manage CPU/GPU coherency if we modify an instobj using the CPU. This patch replaces the legacy and slow PRAMIN access for gk20a instmem with CPU mappings and writes. A LRU list is used to unmap unused mappings after a certain threshold (currently 1MB) of mapped instobjs is reached. This allows mappings to be reused most of the time. Accessing instobjs using the CPU requires to maintain the GPU L2 cache, which we do in the acquire/release functions. This triggers a lot of L2 flushes/invalidates, but most of them are performed on an empty cache (and thus return immediately), and overall context setup performance greatly benefits from this (from 250ms to 160ms on Jetson TK1 for a simple libdrm program). Making L2 management more explicit should allow us to grab some more performance in the future. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau: remove unnecessary usage of object handlesBen Skeggs10-61/+31
No longer required in a lot of cases, as objects are identified over NVIF via an alternate mechanism since the rework. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ltc/gf100: add flush/invalidate functionsAlexandre Courbot5-0/+39
Allow clients to manually flush and invalidate L2. This will be useful for Tegra systems for which we want to write instmem using the CPU. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ltc: add hooks for invalidate and flushAlexandre Courbot3-0/+20
These are useful for systems without a coherent CPU/GPU bus. For such systems we may need to maintain the L2 ourselves. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/timer: re-introduce nvkm_wait_xsec macrosAlexandre Courbot1-0/+10
Reintroduce macros allowing us to test a register against a certain mask, since this is the most common usage pattern for the more generic nvkm_xsec macros and makes the code more concise and readable. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pmu: do not assume a PMU is presentAlexandre Courbot1-1/+1
Some devices may not have a PMU. Avoid a NULL pointer dereference in such cases by checking whether the pointer given to nvkm_pmu_pgob() is valid. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/gem: return only valid domain when there's only oneIlia Mirkin1-2/+3
On nv50+, we restrict the valid domains to just the one where the buffer was originally created. However after the buffer is evicted to system memory, we might move it back to a different domain that was not originally valid. When sharing the buffer and retrieving its GEM_INFO data, we still want the domain that will be valid for this buffer in a pushbuf, not the one where it currently happens to be. This resolves fdo#92504 and several others. These are due to suspend evicting all buffers, making it more likely that they temporarily end up in the wrong place. Cc: stable@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92504 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-10-22drm/msm: Remove local fbdev emulation Kconfig optionArchit Taneja3-21/+3
DRM_MSM_FBDEV config is used to enable/disable fbdev emulation for the msm kms driver. Replace this with the top level DRM_FBDEV_EMULATION config option where applicable. This also prevents build breaks caused by undefined drm_fb_helper_* functions when legacy fbdev support was disabled. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22drm/msm/mdp5: Basic support for MDP5 v1.7 (MSM8996)Stephane Viau6-14/+133
This change adds the basic MDP5 support for MSM8996. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22drm/msm/mdp: Add Software Pixel Extension supportStephane Viau2-31/+128
In order to produce an image, the scalar needs to be fed extra pixels. These top/bottom/left/right values depend on a various of factors, including resolution, scaling type, phase step and initial phase. Pixel Extension are programmed by hardware in most targets - and can be overwritten by software. For some targets (e.g.: msm8996), software *must* program those registers. In order to ease this computation, let's always use bilinear filters, which are easier to program from kernel. Eventually, all of these values will come down from user space for better quality. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22drm/msm/mdp5: Use the newly introduced enum mdp_component_typeStephane Viau1-12/+13
When calculating phase steps, let's use the same enum mdp_component_type in order to ease the readability; 0/1 indexes are a bit confusing and we now have explicit values to index this type of arrays. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22drm/msm/hdmi: Add basic HDMI support for msm8996Stephane Viau2-3/+17
The HDMI controller is new in MDP5 v1.7. As of now, this change doesn't reflect the novelty and only adds the basics so the probe gets triggered. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22drm/msm/mdp5: Avoid printing error messages for optional clocksStephane Viau2-12/+18
The current behavior is to try to get optional clocks and print a dev_err message in case of failure. This looks rather confusing and may increase with the amount of optional clocks. We may need a cleaner way to handle per-device clocks but in the meantime, let's reduce the amount of dev_err messages during the probe. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22drm/msm: Fix IOMMU clean up path in case msm_iommu_new() failsStephane Viau2-0/+9
msm_iommu_new() can fail and this change makes sure that we detect the failure and free the allocated domain before going any further. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22drm/msm/mdp5: remove the cfg pointer from SMP structStephane Viau2-5/+5
We want to make sure we control all the information being passed down to SMP block. Having access to the cfg pointer here may create bad things in the future. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHYHai Li1-4/+2
The current settings for 28nm PHY data lane CFG4 registers do not work with certain panels. This change is to modify them to hw recommended values. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22drm: msm: dsi: Don't attempt changing voltage of switchesBjorn Andersson2-2/+2
In some configurations the supplies are voltage switches and not LDOs, making the set voltage call to fail. Check with the regulator framework if the supply can change voltage before attempting. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22drm/msm: update generated headersRob Clark14-114/+359
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-21drm/amdgpu: change VM size default to 64GBChristian König1-2/+2
That's still small enough to not waste to much memory on PD/PTs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-21drm/amdgpu: add Stoney pci idsSamuel Li1-0/+2
Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-21drm/amdgpu: update the core VI support for StoneySamuel Li3-7/+34
Add core VI enablement for Stoney. Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-21drm/amdgpu: add VCE support for Stoney (v2)Samuel Li2-2/+8
Stoney is VCE 3.x single. v2: Stoney is single pipe like Fiji Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-21drm/amdgpu: add UVD support for StoneySamuel Li1-0/+5
Stoney is UVD 6.x. Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-21drm/amdgpu: add GFX support for Stoney (v2)Samuel Li1-18/+382
Stoney is GFX 8.1. v2: update to latest golden settings Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-21drm/amdgpu: add SDMA support for Stoney (v2)Samuel Li1-0/+28
Stoney is SDMA 3.x. v2: update to latest golden register settings Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-21drm/amdgpu: add DCE support for StoneySamuel Li1-1/+18
Stoney is DCE 11.x. Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-21drm/amdgpu: Update SMC/DPM for StoneySamuel Li2-16/+65
Stoney is SMC 8.x. Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-21drm/amdgpu: add GMC support for StoneySamuel Li1-0/+12
Stoney is GMC 8.x. Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-21drm/amdgpu: add Stoney chip familySamuel Li2-0/+2
Stoney is based on Carrizo with some IP upgrades. Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-21drm: rcar-du: Add support for the R8A7794 DULaurent Pinchart3-3/+29
The R8A7794 DU has a fixed output routing configuration with one RGB output per CRTC and thus lacks the RGB output routing register field. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2015-10-21drm: rcar-du: Add support for the R8A7793 DULaurent Pinchart2-6/+10
The R8A7793 DU is identical to the R8A7791 and thus only requires a new DT compatible string. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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