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2016-04-27arm64: dts: Add initial dts for Hisilicon Hip06 D03 boardKefeng Wang3-1/+344
The Hip06 soc has same cpu topology compared with Hip05, four clusters and each cluster has quard Cortex-A57, but with different IO part, like HNS, SAS and PCI, they are all upgraded. There are also not same in ITS, MBIGEN and SMMU, etc. This patch adds the initial dts for hip06 d03 board. Note, there is no serial, because the soc use LPC uart, the serial node is not needed. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-27arm64: dts: hip05: Add nor flash supportKefeng Wang2-0/+40
This patch is to add support nor-flash. Notice, the pre-defined partitions may not be used. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-27arm64: dts: hip05: fix its node without msi-cellsKefeng Wang1-0/+4
Fix commit abf9c25d55e8 ("arm64: dts: hip05: Append all gicv3 ITS entries"), it forgets the property msi-cell, see arm,gic-v3.txt. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-27arm64: dts: r8a7795: Don't disable referenced optional clocksGeert Uytterhoeven2-4/+2
clk_get() on a disabled clock node will return -EPROBE_DEFER, which can cause drivers to be deferred forever if such clocks are referenced in their devices' clocks properties. Update the various disabled external clock nodes to default to a frequency of 0, but don't disable them, to prevent this. Reported-by: Jürg Billeter <j@bitron.ch> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-27arm64: dts: salvator-x: populate EXTALRWolfram Sang1-0/+4
It can be used for the watchdog. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-27arm64: dts: r8a7795: enable PCIe on Salvator-XPhil Edworthy1-0/+12
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-27arm64: dts: r8a7795: Add PCIe nodesPhil Edworthy1-0/+57
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-26arm64: dts: r8a7795: Don't disable referenced optional scif clockGeert Uytterhoeven1-1/+0
clk_get() on a disabled clock node will return -EPROBE_DEFER, which can cause drivers to be deferred forever if such clocks are referenced in their devices' clocks properties. Update the disabled external scif clock node so that it is not disabled to prevent this. Reported-by: Jürg Billeter <j@bitron.ch> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> [simon: fix for v4.6 extracted from a larger patch targeted at v4.7] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-25arm64: dts: uniphier: add reference clock node for PH1-LD20Masahiro Yamada1-0/+6
Add a master clock node generated by a 25MHz crystal oscillator. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-04-25arm64: dts: uniphier: use Daughter board on PH1-LD20 reference boardMasahiro Yamada2-0/+2
Include the development base board, which is equipped with some devices such as EEPROM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-04-22arm64: dts: NS2 secondary core enablement via PSCILuke Starrett1-22/+9
Declare PSCI-1.0 node and enable CPU_ON method via PSCI. Spin-table memreserve has been removed as well as syscon based reset, as PSCI-1.0 expects reset implementation in firmware. Signed-off-by: Luke Starrett <luke.starrett@broadcom.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-04-20ARM: shmobile: timer: Fix preset_lpj leading to too short delaysGeert Uytterhoeven1-17/+11
On all shmobile ARM SoCs, loop-based delays may complete early, which can be after only 1/3 (Cortex A9) or 1/2 (Cortex A7 or A15) of the minimum required time. This is caused by calculating preset_lpj based on incorrect assumptions about the number of clock cycles per loop: - All of Cortex A7, A9, and A15 run __loop_delay() at 1 loop per CPU clock cycle, - As of commit 11d4bb1bd067f9d0 ("ARM: 7907/1: lib: delay-loop: Add align directive to fix BogoMIPS calculation"), Cortex A8 runs __loop_delay() at 1 loop per 2 instead of 3 CPU clock cycles. On SoCs with Cortex A7 and/or A15 CPU cores, this went unnoticed, as delays use the ARM arch timer if available. R-Car Gen2 doesn't work if the arch timer is disabled. However, APE6 can be used without the arch timer. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-20Revert "ARM: dts: porter: Enable SCIF_CLK frequency and pins"Sjoerd Simons1-13/+0
This reverts commit 19417bd9c511 ("ARM: dts: porter: Enable SCIF_CLK frequency and pins") as according to http://elinux.org/File:R-CarM2-KOELSCH_PORTER-B_PORTER_C_Comparison.pdf the external oscillator for SCIF_CLK is not mounted on the porter boards. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-20ARM: dts: r8a7791: Don't disable referenced optional clocksSjoerd Simons3-4/+3
clk_get on a disabled clock node will return EPROBE_DEFER, which can cause drivers to be deferred forever if such clocks are referenced in their clocks property. Update the various disabled external clock nodes to default to a frequency of 0, but don't disable them to prevent this. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-15arm64: dts: Add L2 cache topology to Hi6220Leo Yan1-0/+16
This patch adds the L2 cache topology on Hi6220. Hi6220 has two clusters, every cluster has 512KiB L2 cache (32KiB x 16 ways). Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: register Hi6220's thermal zone for power allocatorLeo Yan1-0/+35
With profiling Hi6220's power modeling so get dynamic coefficient and sustainable power. So pass these parameters from DT. Now enable power allocator with only one actor for CPU part, so directly use cluster0's thermal sensor for monitoring temperature. Reviewed-by: Javi Merino <javi.merino@arm.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: register Hi6220's thermal sensorLeo Yan1-0/+9
Bind thermal sensor driver for Hi6220. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: add wifi nodes support for hi6220-hikeyGuodong Xu1-0/+29
Add wifi nodes support for hi6220-hikey Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: add dwmmc nodes for hi6220Xinwei Kong1-0/+52
Add all three dwmmc nodes description for hi6220 Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: hikey: Add hi655x pmic dts nodeChen Feng1-1/+86
Add the mfd hi655x dts node and regulator support on hi6220 platform. Signed-off-by: Chen Feng <puck.chen@hisilicon.com> Signed-off-by: Fei Wang <w.f@huawei.com> Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Reviewed-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: add LED nodes for hi6220-hikeyGuodong Xu1-0/+41
Add LED nodes for hi6220-hikey. There are total 6 LEDs on HiKey. Four general purposed, one for WiFi activity, and one for Bluetooth activity. Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: hi6220: add pinctrl for uarts and enable themGuodong Xu2-0/+21
Add pinctrl for uart2 uart3 and uart4. Enable uart1 uart2 and uart3. Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: add Hi6220's stub clock nodeLeo Yan1-0/+56
Enable SRAM node and stub clock node for Hi6220, which uses mailbox channel 1 for CPU's frequency change. Furthermore, add the CPU clock phandle in CPU's node and using operating-points-v2 to register operating points. So can be used by cpufreq-dt driver. Signed-off-by: Leo Yan <leo.yan@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: add mailbox node for Hi6220Leo Yan1-0/+8
This patch add device mailbox node for Hi6220 in DT. Signed-off-by: Leo Yan <leo.yan@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: Add hi6220 usb nodeZhangfei Gao1-0/+32
Add USB nodes for Hi6220 Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: hikey: enable i2c0 and i2c1 for working with mezzanine boardsGuodong Xu1-0/+8
In HiKey board dts file, enable i2c0 and i2c1 for working with 96boards' LS mezzanine. Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: add all hi6220 i2c nodesXinwei Kong1-0/+33
This patch adds all I2C nodes for the Hi6220 SoC. This hi6220 Soc use this I2C IP of Synopsys Designware for HiKey board. Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com> Signed-off-by: Chen Feng <puck.chen@hisilicon.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: add Hi6220 spi configuration nodesZhong Kaihua3-0/+42
Add Hi6220 spi configuration nodes. Disable by default in hi6220.dtsi and enable it in board dts for usage of 96boards LS mezzanine board. Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com> Signed-off-by: Guodong Xu <guodong.xu@linaro.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: add Hi6220 pinctrl configuration nodesZhong Kaihua4-0/+821
Add Hi6220 pinctrl configuration nodes Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: Add Hi6220 gpio configuration nodesZhong Kaihua1-0/+239
Add Hi6220 gpio configuration nodes Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com> Signed-off-by: Kong Xinwei <kong.kongxinwei@hisilicon.com> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: enable idle states for Hi6220Leo Yan1-0/+31
Add cpu and cluster level's low power state for Hi6220. Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: add sp804 timer node for Hi6220Leo Yan1-0/+11
Add sp804 timer for hi6220, so it can be used as broadcast timer. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: dts: Reserve memory regions for hi6220Leo Yan1-4/+12
On Hi6220, below memory regions in DDR have specific purpose: 0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime; 0x06df,f000 - 0x06df,ffff: For mailbox message data; 0x0740,f000 - 0x0740,ffff: For MCU firmware's section; 0x3e00,0000 - 0x3fff,ffff: For OP-TEE. This patch reserves these memory regions in DT. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15arm64: tegra: Enable cros-ec and charger on SmaugRhyland Klein1-0/+27
Add nodes for the ChromeOS Embedded Controller and for the gas gauge connected to the I2C bus that it controls. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-15arm64: dts: juno: Add external expansion bus to DTBrian Starkey1-0/+10
The Juno development platform has an external expansion bus which can be used for additional hardware (e.g. LogicTile Express daughterboards). Add this bus to the Juno base device-tree. Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2016-04-14arm64: dts: apm: Fix compatible string for X-Gene 2 SATA controller DTS nodeRameshwar Prasad Sahu1-3/+3
Fix X-Gene SATA controller compatible string for Merlin board. Signed-off-by: Rameshwar Prasad Sahu <rsahu@apm.com> Acked-by: Suman Tripathi <stripathi@apm.com>
2016-04-13arm64: dts: Add dts files for LG Electronics's lg1312 SoCChanho Min4-0/+393
Add initial dtsi file to support lg1312 SoC which based on Cortex-A53. Also add dts file to support lg1312 reference board which based on lg1312 SoC. Signed-off-by: Chanho Min <chanho.min@lge.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-04-13arm64: dts: Add ARM PL022 SPI DT nodes for NS2Anup Patel2-0/+67
We have two ARM PL022 SPI instances in NS2 SoC. On NS2 SVK, one of the ARM PL022 SPI host has Silabs si3226x slic connected to chip-select #0 whereas second ARM PL022 SPI host has Atmel AT25 EEPROM connected to chip-select #0. This patch adds ARM PL022, Silabs si3226x, and Atmel AT25 DT nodes in NS2 DT and NS2 SVK DT respectively. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-04-13arm64: dts: Move NS2 clock DT nodes to separate DT fileAnup Patel2-78/+108
For more readabilty and consistency with other Broadcom SoCs, we move all NS2 clock DT nodes from main SoC DT file to a separate DT file. We also update the license header in ns2.dtsi as-per new Broadcom convention. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-04-13arm64: dts: Add maintenance interrupt for GIC in NS2 DTAnup Patel1-0/+2
The KVM ARM64 requires GIC maintenance interrupt for VGIC emulation so this patch adds the missing "interrupts" attribute to GIC node in NS2 DT. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-04-13arm64: dts: Add ARM PL330 DMA DT node for NS2Anup Patel1-0/+19
We have one ARM PL330 DMA instance with 8 channels in NS2 SoC. Let's enable it for NS2 in NS2 DT. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Pramod KUMAR <pramodku@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-04-13arm64: dts: Add nodes for pdma0 and pdma1 for exynos7Alim Akhtar1-0/+29
This patch adds device tree nodes for pdma0 and pdma1 controllers found on exynos7 SoCs. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
2016-04-12arm64: tegra: Add pinmux for Smaug boardRhyland Klein1-0/+1271
Add pinmux node for Tegra210 Smaug board. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Add stdout-path for various boardsJon Hunter2-1/+8
For Tegra boards, the device-tree alias serial0 is used for the console and so add the stdout-path information so that the console no longer needs to be passed via the kernel boot parameters. For tegra132-norrin the alias serial0 is not defined and so add this. This has been tested on tegra132-norrin and tegra210-p2371-0000. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Remove unused #power-domain-cells propertyJon Hunter1-2/+0
Remove the "#power-domain-cells" property which was incorrectly included by commit e53095857166 ("arm64: tegra: Add Tegra210 support"). Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Add gpio-keys nodes for SmaugRhyland Klein1-0/+43
Add gpio-keys nodes for the volumn controls, lid switch, tablet mode and power button. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> [treding@nvidia.com: use symbolic names for input types and codes] [treding@nvidia.com: use wakeup-source instead of gpio-key,wakeup] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Enable power and volume keys on Jetson TX1Laxman Dewangan1-0/+26
Add a gpio-keys device tree node to represent the Power, Volume Up and Volume Down keys found on Jetson TX1. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Add support for Google Pixel CJon Hunter2-0/+84
Add initial device-tree support for Google Pixel C (a.k.a. Smaug) based upon Tegra210 SoC with 3 GiB of LPDDR4 RAM. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Tested-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Replace legacy *,wakeup property with wakeup-sourceSudeep Holla1-2/+2
Though the keyboard and other driver will continue to support the legacy "gpio-key,wakeup", "nvidia,wakeup-source" boolean property to enable the wakeup source, "wakeup-source" is the new standard binding. This patch replaces all the legacy wakeup properties with the unified "wakeup-source" property in order to avoid any further copy-paste duplication. Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Fix copy/paste typo in several DTS includesThierry Reding2-2/+2
The comment about the 8250 vs. APB DMA-enabled UART devices that was added for Tegra20 and Tegra30 in commit b6551bb933f9 ("ARM: tegra: dts: add aliases and DMA requestor for serial controller") introduced a typo that has since spread to various other DTS include files. Fix all occurrences of this typo. Suggested-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
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