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2018-07-06clk: aspeed: Fix SDCLK nameLei YU2-2/+2
The SDCLK was named SDCLKCLK, and no one has used this yet. Fix it. Signed-off-by: Lei YU <mine260309@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: pxa: export 32kHz PLLRobert Jarzmik4-9/+14
This clock is especially used by the RTC driver, so export it so that devicetree users can use it. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: Add driver for MAX9485Daniel Mack3-0/+394
This patch adds a driver for MAX9485, a programmable audio clock generator. The device requires a 27.000 MHz clock input. It can provide a gated buffered output of its input clock and two gated outputs of a PLL that can generate one out of 16 discrete frequencies. There is only one PLL however, so the two gated outputs will always have the same frequency but they can be switched individually. The driver for this device exposes 4 clocks in total: - MAX9485_MCLKOUT: A gated, buffered output of the input clock - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete frequencies - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT Some PLL output frequencies can be achieved with different register settings. The driver will select the one with lowest jitter in such cases. Signed-off-by: Daniel Mack <daniel@zonque.org> [sboyd@kernel.org: Use local variable for val in max9485_clkout_recalc_rate() and shorten line of max9485_of_clk_get()] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: ingenic: Add missing flag for UDC clockPaul Cercueil1-1/+1
The UDC clock of the JZ4740 SoC can be gated, but the data structure representing it was missing the CGU_CLK_GATE flag to make it work. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: ingenic: Fix incorrect data for the i2s clockPaul Cercueil1-1/+1
The register field for configuring the divider for the i2s clock occupies the bits [8-0], which means 9 bits and not 8. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06dts: clk: add devicetree bindings for MAX9485Daniel Mack2-0/+77
This patch adds the devicetree bindings for MAX9485, a programmable audio clock generator. Signed-off-by: Daniel Mack <daniel@zonque.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: at91: add I2S clock mux driverCodrin Ciubotariu3-0/+121
This driver is a simple muxing driver that controls the I2S's clock input by using syscon/regmap to change the parent. The available inputs can be peripheral clock and generated clock. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> [sboyd@kernel.org: Fix SPDX tag comment style] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06dt-bindings: clk: at91: add an I2S mux clockCodrin Ciubotariu1-0/+35
The I2S mux clock can be used to select the I2S input clock. The available parents are the peripheral and the generated clocks. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: socfpga: stratix10: fix the sdmmc_free_clk muxDinh Nguyen1-1/+1
The first parent of the sdmmc_free_clk should be the main_sdmmc_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: socfpga: stratix10: fix the parents of mpu_free_clkDinh Nguyen1-1/+6
Add a clock mux that is used as a parent for the mpu_free_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-03clk: qcom: Enable clocks which needs to be always on for SDM845Amit Nischal2-4/+41
There are certain clocks which needs to be always enabled for system operation. Add support for the same by adding 'CLK_IS_CRITICAL' flag for such clocks. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-29clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SELPhilipp Puschmann1-1/+1
q/dl datasheets list the 5th selection value for ck01_sel as video_27M_clk_root. By replacing the dummy value we then can set IMX6QDL_CLK_VIDEO_27M as parent for IMX6QDL_CLK_CKO1_SEL. Signed-off-by: Philipp Puschmann <pp@emlix.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-29clk: imx6ul: remove clks_init_on arrayAnson Huang1-17/+6
Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. ARM clock is busy divider type which has the CLK_IS_CRITICAL flag set by default when registered. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-29clk: imx6ul: add GPIO clock gatesAnson Huang2-1/+12
i.MX6UL has GPIO clock gates in CCM CCGR, add them into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-29dt-bindings: clock: imx6ul: Do not change the clock definition orderFabio Estevam1-21/+19
Commit f5a4670de966 ("clk: imx: Add new clo01 and clo2 controlled by CCOSR") introduced the CLK_CLKO definitions, but didn't put them at the end of the list, which may cause dtb breakage when running an old dtb with a newer kernel. In order to avoid that, simply add the new CLK_CKO clock definitions at the end of the list. Fixes: f5a4670de966 ("clk: imx: Add new clo01 and clo2 controlled by CCOSR") Reported-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-29clk-si514, clk-si544: Implement prepare/unprepare/is_prepared operationsMike Looijmans2-2/+74
This adds prepare/unprepare/is_prepared functionality to the drivers for the SI544 and SI514 chips, allowing the clock output to be disabled when the clock is not in use. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-25clk: renesas: Renesas R9A06G032 clock driverMichel Pollet3-0/+900
This provides a clock driver for the Renesas R09A06G032. This uses a structure derived from both the R-Car Gen2 driver as well as the renesas-cpg-mssr driver. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>