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2012-06-14ARM: LPC32xx: Add dt settings to the at25 nodeAlexandre Pereira da Silva1-0/+21
Add the reg, cs-gpios and max-frequencies that are needed for spi device registry in phy3250. Adds also the pl022 internal transfers details via dt Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Build arch dtbsAlexandre Pereira da Silva1-0/+1
Add ea3250.dtb and phy3250.dtb to the list of dtbs to be built Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Fix lpc32xx.dtsi status property: "disable" -> "disabled"Roland Stigge1-7/+7
This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Remove mach specific ARCH_NR_GPIOS, use defaultRoland Stigge1-2/+0
ARCH_NR_GPIOS was defined statically to include exactly all SoC specific GPIOs. Now if additional GPIOs need to be added dynamically, e.g. via DT, none are available. Removing the mach specific setting, leaving ARCH_NR_GPIOS to the default of 256 (currently in include/asm-generic/gpio.h). Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: High Speed UART configuration via DTRoland Stigge2-5/+15
This patch fixes the DTS files for the High Speed UARTs 1, 2 and 7 of the LPC32xx SoC, adjusting the compatible strings, adding interrupts and status configuration. On the PHY3250 reference board, UART2 is enabled. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: DT conversion of Standard UARTsRoland Stigge5-126/+35
This patch switches from static serial driver initialization to devicetree configuration. This way, the Standard UARTs of the LPC32xx SoC can be enabled individually via DT. E.g., instead of Kconfig configuration, the phy3250.dts activates UARTs 3 and 5. Signed-off-by: Roland Stigge <stigge@antcom.de> Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: DTS adjustment for using pl18x primecellRoland Stigge2-1/+10
This patch adjusts the dts files to reference the pl18x primecell driver correctly. Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Add MMC controller supportRoland Stigge1-4/+39
This patch adds support for the MMC controller of the LPC32xx SoC to the platform initialization via the pl08x primecell driver. Lacking more complete DT support, done via DT auxdata. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: Defconfig updateRoland Stigge1-6/+18
This defconfig update for the LPC32xx SoC platform adds the new drivers in v3.5 and drivers typically used in systems with the LPC32xx chip. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: Clock adjustment for key matrix controllerRoland Stigge1-1/+1
The clock.c file needs to be changed to match the automatic device name to its clock. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com>
2012-06-14ARM: LPC32xx: DTS adjustment for key matrix controllerRoland Stigge2-0/+11
This patch connects the lpc32xx-key driver to the LPC32xx platform (via lpc32xx.dtsi), and more specifically to the reference board via its dts file. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>