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2021-06-27clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepareJonathan Marek1-1/+1
Caught this when looking at alpha-pll code. Untested but it is clear that this was intended to write to PLL_CAL_L_VAL and not PLL_ALPHA_VAL. Fixes: 691865bad627 ("clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210609022852.4151-1-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: Add camera clock controller driver for SM8250Jonathan Marek3-0/+2464
Add support for the camera clock controller found on SM8250. Based on the downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Robert Foss <robert.foss@linaro.org> Link: https://lore.kernel.org/r/20210609022051.2171-4-jonathan@marek.ca [sboyd@kernel.org: Add UL to avoid decimal problems] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: add QCOM SM8250 camera clock bindingsJonathan Marek2-0/+206
Add device tree bindings for camera clock controller for Qualcomm Technology Inc's SM8250 SoC. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210609022051.2171-3-jonathan@marek.ca Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: clk-alpha-pll: add support for zonda pllJonathan Marek2-0/+180
Ported over from the downstream driver. Will be used by SM8250 CAMCC. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210609022051.2171-2-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk/qcom: Remove unused variablesPu Lehui1-23/+0
Fix gcc '-Wunused-const-variable' warnings: drivers/clk/qcom/gcc-mdm9607.c:122:37: warning: 'gcc_xo_gpll0_gpll1' defined but not used [-Wunused-const-variable=] drivers/clk/qcom/gcc-mdm9607.c:116:32: warning: 'gcc_xo_gpll0_gpll1_map' defined but not used [-Wunused-const-variable=] drivers/clk/qcom/gcc-mdm9607.c:42:37: warning: 'gcc_xo_sleep' defined but not used [-Wunused-const-variable=] drivers/clk/qcom/gcc-mdm9607.c:37:32: warning: 'gcc_xo_sleep_map' defined but not used [-Wunused-const-variable=] Let's remove them. Signed-off-by: Pu Lehui <pulehui@huawei.com> Link: https://lore.kernel.org/r/20210609061848.87415-1-pulehui@huawei.com Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: smd-rpmcc: Add support for MSM8226 rpm clocksBartosz Dudziak1-0/+1
Add compatible for rpm smd clocks, PMIC and bus clocks which are required on MSM8226 for clients to vote on. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Link: https://lore.kernel.org/r/20210605104040.12960-1-bartosz.dudziak@snejp.pl Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: gcc: Add support for Global Clock controller found on MSM8226Bartosz Dudziak1-7/+162
Modify existing MSM8974 driver to support MSM8226 SoC. Override frequencies which are different in this older chip. Register all the clocks to the framework for the clients to be able to request for them. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Link: https://lore.kernel.org/r/20210418122909.71434-3-bartosz.dudziak@snejp.pl Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: qcom: Add MSM8226 GCC clock bindingsBartosz Dudziak1-2/+3
Add compatible device strings and the include files for the MSM8226 GCC. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Link: https://lore.kernel.org/r/20210418122909.71434-2-bartosz.dudziak@snejp.pl Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: Add SM6125 (TRINKET) GCC driverKonrad Dybcio3-0/+4198
Add the clocks supported in global clock controller, which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20210605121040.282053-2-martin.botka@somainline.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> [sboyd@kernel.org: Mark gcc_sm6125_hws array static] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clk: qcom: gcc-sm6125: Document SM6125 GCC driverMartin Botka2-0/+312
Document the newly added SM6125 GCC driver. Signed-off-by: Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20210605121040.282053-1-martin.botka@somainline.org Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: gcc: Add support for a new frequency for SC7280Taniya Das1-0/+1
There is a requirement to support 52MHz for qup clocks for bluetooth usecase, thus update the frequency table to support the frequency. Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1624449471-9984-1-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-25clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulatorAlexandru Ardelean1-2/+2
The purpose of the device-managed functions is to bind the life-time of an object to that of a parent device object. This is not the case for the 'vdd-cpu' regulator in this driver. A reference is obtained via devm_regulator_get() and immediately released with devm_regulator_put(). In this case, the usage of devm_ functions is slightly excessive, as the un-managed versions of these functions is a little cleaner (and slightly more economical in terms of allocation). This change converts the devm_regulator_{get,put}() to regulator_{get,put}() in the get_alignment_from_regulator() function of this driver. Signed-off-by: Alexandru Ardelean <aardelean@deviqon.com> Link: https://lore.kernel.org/r/20210624084737.42336-1-aardelean@deviqon.com Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-22clk: keystone: syscon-clk: Add support for AM64 specific epwm-tbclkLokesh Vutla1-0/+17
AM64 has 9 instances of EPWM modules. And each instance has a clk to Timer-Base sub-module that can be controlled by Control module. Update the driver with all the 9 instance of clocks associated to ti,am64-epwm-tbclk. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210528045743.16537-3-lokeshvutla@ti.com Reviewed-by: Tero Kristo <kristo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-22dt-bindings: clock: ehrpwm: Add support for AM64 specific compatibleLokesh Vutla1-1/+3
Introduce AM64 specific compatible for epwm time-base sub-module clock. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210528045743.16537-2-lokeshvutla@ti.com Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Tero Kristo <kristo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-14clk: imx8mq: remove SYS PLL 1/2 clock gatesLucas Stach2-57/+18
Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks the uSDHC module which is sporadically unable to enumerate devices after this change. Also it makes AMP clock management harder with no obvious benefit to Linux, so just revert the change. Link: https://lore.kernel.org/r/20210528180135.1640876-1-l.stach@pengutronix.de Fixes: b04383b6a558 ("clk: imx8mq: Define gates for pll1/2 fixed dividers") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: Do not enable runtime PM for CPU clksNitin Garg1-12/+18
Since CPU clocks are managed by CPUFREQ and ATF, do not enable runtime PM otherwise rpm gets out of status as cpufreq also manages clock states. Signed-off-by: Nitin Garg <nitin.garg@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: add parent save and restoreDong Aisheng1-1/+28
Add clock parent save and restore. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: Only save DC SS clock using non-cached clock rateAnson Huang1-1/+8
Display sub-system has special clock settings in SCFW, the bypassed clock is used instead of PLL in Linux kernel clock tree, so when saving clock rate, need to save non-cached clock rate for Display sub-system's bypass clocks, and other clocks still use the cached clock rate which is with runtime PM ON. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: Add A72 frequency scaling supportAnson Huang1-1/+3
Add A72 clock to support cpufreq on A72 cluster. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: Add A53 frequency scaling supportAnson Huang1-2/+2
Add i.MX8QM cpufreq support for A53 cluster. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: bypass pi_pll enable status restoreDong Aisheng1-1/+1
PI PLL does not support enable/disable. So bypass it's enable status restore. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: detach pd if can't power upDong Aisheng1-0/+1
detach pd if can't power up as it may be allocated to a differet partition. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: bypass cpu clock save and restoreDong Aisheng1-0/+10
CPU clock is managed by ATF. No need save and restore. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: add parallel port clock opsGuoniu.zhou1-0/+8
Because digital pll for parallel interface is on by default, and not provide enable/disable function by scu, so add the related ops for this kind of clocks. Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: add more scu clocksDong Aisheng1-2/+150
Add more scu clocks used by i.MX8 platforms. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: add enet rgmii gpr clocksDong Aisheng1-4/+18
enet tx clk actually is sourced from a gpr divider, not default enet clk. Add enet grp clocks for user to use correctly. Cc: Abel Vesa <abel.vesa@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx8qm: add clock valid resource checkingDong Aisheng4-1/+119
Add imx8qm clock valid resource checking mechanism Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx8qxp: add clock valid checking mechnismDong Aisheng5-8/+137
clk-imx8qxp is a common SCU clock driver used by both QM and QXP platforms. The clock numbers vary a bit between those two platforms. This patch introduces a mechanism to only register the valid clocks for one platform by checking the clk resource id table. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: add gpr clocks supportDong Aisheng2-0/+215
SCU clock protocol supports a few clocks based on GPR controller registers including mux/divider/gate. Add a generic clock register API to support them all. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: remove legacy scu clock binding supportDong Aisheng3-263/+81
Legacy scu clock binding are not maintained anymore, it has a very limited clocks supported during initial upstreaming and obviously unusable by products. So it's meaningless to keep it in kernel which worse the code readability. Remove it to keep code much cleaner. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14dt-bindings: arm: imx: scu: drop deprecated legacy clock bindingDong Aisheng1-4/+2
The legacy clock binding are not maintained anymore. It has only a very preliminary supported clocks during initial upstream and meaningless for users. So drop it from binding doc now. Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14dt-bindings: arm: imx: scu: fix naming typo of clk compatible stringDong Aisheng1-2/+2
There is a typo in binding doc that the name of compatible string of scu clock should be "fsl,xxx-clk" rather than "fsl,xxx-clock". In reality, both example and dts using "fsl,xxx-clk", so fixing the doc is enough. Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: Remove the audio ipg clock from imx8mpJacky Bai1-1/+0
There is no audio ipg clock on i.MX8MP, so remove this from the clock driver. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-10clk: renesas: Add support for R9A07G044 SoCLad Prabhakar5-0/+141
Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-10clk: renesas: Add CPG core wrapper for RZ/G2L SoCLad Prabhakar4-0/+883
Add CPG core wrapper for RZ/G2L family. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>