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2021-04-01ARM: mstar: Add the external clocks to the base dstiDaniel Palmer1-0/+15
All of the currently known MStar/SigmaStar ARMv7 SoCs have an "xtal" clock input that is usually 24MHz and an "RTC xtal" that is usually 32KHz. The xtal input has to be connected to something so it's enabled by default. The MSC313 and MSC313E do not bring the RTC clock input out to the pins so it's impossible to connect it. The SSC8336 does bring the input out to the pins but it's not always actually connected to something. The RTC node needs to always be present because in the future the nodes for the clock muxes will refer to it even if it's not usable. The RTC node is disabled by default and should be enabled at the board level if the RTC input is wired up. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Link: https://lore.kernel.org/r/20210301123542.2800643-3-daniel@0x0f.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-01ARM: mstar: Select MSTAR_MSC313_MPLLDaniel Palmer1-0/+1
All of the ARCH_MSTARV7 chips have an MPLL as the source for peripheral clocks so select MSTAR_MSC313_MPLL. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Link: https://lore.kernel.org/r/20210301123542.2800643-2-daniel@0x0f.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-01ARM: dts: stm32: Add PTP clock to Ethernet controllerKurt Kanzenbach1-0/+2
Add the PTP clock to the Ethernet controller. Otherwise, the driver uses the main clock to derive the PTP frequency which is not necessarily the correct one. Tested with linuxptp on Olimex STMP1-OLinuXino-LIME2. Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-01ARM: dts: stm32: Enable crc1 and cryp1 where applicable on DHSOMMarek Vasut5-0/+20
Enable the CRC accelerator on all STM32MP15xx DHSOM based systems and CRYP accelerator on all STM32MP15x[CF] DHSOM based systems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-01ARM: dts: stm32: Update GPIO line names on PicoITXMarek Vasut1-6/+6
Use more specific custom GPIO line names which denote exactly where the GPIO came from, i.e. the base board. Also, update the new blank GPIO line names set up by stm32mp15xx-dhcom-som.dtsi back to their original values. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-01ARM: dts: stm32: Update GPIO line names on DRC02Marek Vasut1-6/+6
Use more specific custom GPIO line names which denote exactly where the GPIO came from, i.e. the base board. Also, update the new blank GPIO line names set up by stm32mp15xx-dhcom-som.dtsi back to their original values. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-01ARM: dts: stm32: Fill GPIO line names on AV96Marek Vasut1-0/+35
Fill in the custom GPIO line names used by DH. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-01ARM: dts: stm32: Fill GPIO line names on DHCOM SoMMarek Vasut1-0/+60
Fill in the custom GPIO line names used by DH on the DHCOM SoM. The GPIO line names are in accordance to DHCOM Design Guide R04 available at [1], section 3.9 GPIO. [1] https://wiki.dh-electronics.com/images/5/52/DOC_DHCOM-Design-Guide_R04_2018-06-28.pdf Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-01dt-bindings: serial: stm32: Use 'type: object' instead of false for 'additionalProperties'dillon min1-1/+2
To use additional properties 'bluetooth' on serial, need replace false with 'type: object' for 'additionalProperties' to make it as a node, else will run into dtbs_check warnings. 'arch/arm/boot/dts/stm32h750i-art-pi.dt.yaml: serial@40004800: 'bluetooth' does not match any of the regexes: 'pinctrl-[0-9]+' Fixes: af1c2d81695b ("dt-bindings: serial: Convert STM32 UART to json-schema") Reported-by: kernel test robot <lkp@intel.com> Tested-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: dillon min <dillon.minfei@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1616757302-7889-8-git-send-email-dillon.minfei@gmail.com Signed-off-by: dillon min <dillon.minfei@gmail.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-01ARM: stm32: Add a new SoC - STM32H750dillon min1-0/+1
The STM32H750 is a Cortex-M7 MCU running at 480MHz and containing 128KBytes internal flash, 1MiB SRAM. Signed-off-by: dillon min <dillon.minfei@gmail.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-01ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6dillon min4-0/+325
This patchset has following changes: - introduce stm32h750.dtsi to support stm32h750 value line - add pin groups for usart3/uart4/spi1/sdmmc2 - add stm32h750i-art-pi.dtb (arch/arm/boot/dts/Makefile) - add stm32h750-art-pi.dts to support art-pi board art-pi board component: - 8MiB qspi flash - 16MiB spi flash - 32MiB sdram - ap6212 wifi&bt&fm the detail board information can be found at: https://art-pi.gitee.io/website/ Signed-off-by: dillon min <dillon.minfei@gmail.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-01ARM: dts: stm32: fix i2c node typo in stm32h743Alexandre Torgue1-2/+2
Replace upper case by lower case in i2c nodes name. Signed-off-by: dillon min <dillon.minfei@gmail.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-01ARM: dts: stm32: add new instances for stm32h743 MCUAlexandre Torgue1-0/+31
Some instances are missing in current support of stm32h743 MCU. This commit adds usart3/uart4 and sdmmc2 support. Signed-off-by: dillon min <dillon.minfei@gmail.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-01ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750dillon min5-308/+330
This patch is intend to add support stm32h750 value line, just add stm32h7-pinctrl.dtsi for extending, with following changes: - rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi - move 'pin-controller' from stm32h7-pinctrl.dtsi to stm32h743.dtsi, to fix make dtbs_check warrnings arch/arm/boot/dts/stm32h750i-art-pi.dt.yaml: soc: 'i2c@40005C00', 'i2c@58001C00' do not match any of the regexes: '@(0|[1-9a-f][0-9a-f]*)$', '^[^@]+$', 'pinctrl-[0-9]+' Signed-off-by: dillon min <dillon.minfei@gmail.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-01dt-bindings: arm: stm32: Add compatible strings for ART-PI boarddillon min1-0/+4
Art-pi based on stm32h750xbh6, with following resources: -8MiB QSPI flash -16MiB SPI flash -32MiB SDRAM -AP6212 wifi, bt, fm detail information can be found at: https://art-pi.gitee.io/website/ Signed-off-by: dillon min <dillon.minfei@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-01Documentation: arm: stm32: Add stm32h750 value line docdillon min2-0/+35
This patchset add support for soc stm32h750, stm32h750 has mirror different from stm32h743 item stm32h743 stm32h750 flash size: 2MiB 128KiB adc: none 3 crypto-hash: none aes/hamc/des/tdes/md5/sha detail information can be found at: https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html Signed-off-by: dillon min <dillon.minfei@gmail.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-03-30arm64: dts: intel: adjust qpsi read-delay propertyDinh Nguyen1-1/+1
The "cnds,read-delay" value needs to be 2 for the Agilex devkit. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-30arm64: dts: intel: socfpga_agilex_socdk_nand: align LED node names with dtschemaKrzysztof Kozlowski1-3/+3
Align the LED node names with dtschema to silence dtbs_check warnings like: leds: 'hps0', 'hps1', 'hps2' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-30arm64: dts: intel: socfpga_agilex: align node names with dtschemaKrzysztof Kozlowski1-4/+4
Align the NAND, GIC and UART node names with dtschema to silence dtbs_check warnings like: arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dt.yaml: intc@fffc1000: $nodename:0: 'intc@fffc1000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dt.yaml: serial0@ffc02000: $nodename:0: 'serial0@ffc02000' does not match '^serial(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-30arm64: dts: intel: socfpga_agilex: use defined for GIC interruptsKrzysztof Kozlowski1-55/+82
Use human-readable defines for GIC interrupt type and flag, instead of hard-coding the numbers. It makes review easier. No functional change. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-30arm64: dts: intel: socfpga_agilex: move usbphy out of soc nodeKrzysztof Kozlowski1-5/+5
The usual usb-nop-xceiv USB phy node should be under root node, to fix dtc warning: arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:472.21-476.5: Warning (simple_bus_reg): /soc/usbphy@0: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-30arm64: dts: intel: socfpga_agilex: remove default status=okayKrzysztof Kozlowski1-1/+0
New nodes are okay by default. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-30arm64: dts: intel: socfpga_agilex: move timer out of soc nodeKrzysztof Kozlowski1-9/+9
The ARM architected timer is part of ARM CPU design therefore by convention it should not be inside the soc node. This also fixes dtc warning like: arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:410.9-416.5: Warning (simple_bus_reg): /soc/timer: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-30arm64: dts: intel: socfpga_agilex: move clocks out of soc nodeKrzysztof Kozlowski1-28/+28
The clocks are usually not part of the SoC but provided on the board (external oscillators). Moving them out of soc node fixes dtc warning: arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:111.10-137.5: Warning (simple_bus_reg): /soc/clocks: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-30arm64: dts: intel: socfpga: override clocks by labelKrzysztof Kozlowski3-24/+12
Using full paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-30ARM: dts: ux500: Add Cypress CTTYSP touch to TVK UIBLinus Walleij1-0/+46
The TVK1281618 R3 UIB has a Cypress CTTYSP touchscreen. Add it to the device tree file. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-30ARM: dts: ux500: Bump AUX1 voltageLinus Walleij1-2/+2
The voltage default on the AB8500 VAUX1 regulator is way too low and does not correspond to the setting in the vendor tree. This should be 2.8-3.3 V not 2.5-2.9 V or things like the HREFP520 touchscreen will not work. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-30ARM: dts: imx6: pbab01: Set USB OTG port to peripheralStefan Riedmueller1-0/+1
Due to a hardware bug preventing the correct detection if the ID pin the USB OTG port cannot be used in otg mode. It can either be set to host or peripheral. Set it to peripheral so vbus is disabled by default. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-30ARM: dts: imx6: pfla02: Fix USB vbus enable pinmuxingStefan Riedmueller1-4/+4
The pinmuxing for the enable pin of the usbh1 node is wrong. It needs to be muxed as GPIO. While at it, move the pinctrl to the vbus regulator since it is actually the regulator enable pin. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: broadcom: bcm4908: add Ethernet MAC addrRafał Miłecki2-0/+28
On most BCM4908 devices MAC address can be read from the bootloader binary section containing device settings. Use NVMEM to describe that. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-03-29ARM: dts: BCM5301X: Set Linksys EA9500 power LEDRafał Miłecki1-0/+1
Set Linux default trigger to default on, just like it's normally done for power LEDs. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-03-29ARM: dts: BCM5301X: Fix Linksys EA9500 partitionsRafał Miłecki1-9/+7
Partitions are basically fixed indeed but firmware ones don't have hardcoded function ("firmware" vs "failsafe"). Actual function depends on bootloader configuration. Use a proper binding for that. While at it fix numbers formatting to avoid: arch/arm/boot/dts/bcm47094-linksys-panamera.dt.yaml: partitions: 'partition@1F00000' does not match any of the regexes: '^partition@[0-9a-f]+$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/mtd/partitions/linksys,ns-partitions.yaml Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-03-29ARM: dts: stm32: enable the analog filter for all I2C nodes in stm32mp151Alain Volmat1-0/+6
Enable the analog filter for all I2C nodes of the stm32mp151. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-03-29arm64: dts: fsl-ls1028a-kontron-sl28: add rtc0 aliasMichael Walle1-1/+2
For completeness, add the rtc0 alias. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: ls1028a: move rtc alias to individual boardsMichael Walle4-4/+3
The aliases are board-specific and shouldn't be included in the common SoC dtsi. Move them over to the boards. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: fsl-ls1028a-kontron-sl28: combine unused partitionsMichael Walle1-19/+1
The failsafe partitions for the DP firmware and for AT-F are unused. If AT-F will ever be supported in the failsafe mode, then it will be a FIT image. Thus fold the unused partitions into the failsafe bootloader one to have enough storage if the bootloader image will grow. While at it, remove the reserved partition. It served no purpose other than having no hole in the map. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: fsl-ls1028a-kontron-sl28: move MTD partitionsMichael Walle1-45/+49
Move the MTD partitions to the partitions subnode. This is the new way to specify the partitions, see Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: imx8mp-evk: Improve the Ethernet PHY descriptionFabio Estevam1-0/+2
According to the datasheet RTL8211, it must be asserted low for at least 10ms and at least 72ms "for internal circuits settling time" before accessing the PHY registers. Add properties to describe such requirements. Reported-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: imx8mq-librem5-r3: Mark buck3 as always onSebastian Krzyszkowiak1-0/+4
Commit 99e71c029213 ("arm64: dts: imx8mq-librem5: Don't mark buck3 as always on") removed always-on marking from GPU regulator, which is great for power saving - however it introduces additional i2c0 traffic which can be deadly for devices from the Dogwood batch. To workaround the i2c0 shutdown issue on Dogwood, this commit marks buck3 as always-on again - but only for Dogwood (r3). Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: imx8mq-librem5: Hog the correct gpioGuido Günther1-1/+2
There was an additional alias in the specifier it hogged line 27 instead of line 1. Signed-off-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: lx2160a-clearfog-itx: add SFP supportRussell King2-0/+88
Add 2x2 SFP+ cage support for clearfog-itx boards. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UARTTeresa Remmet1-6/+6
With the first redesign the debug UART had changed from UART2 to UART1. As the first hardware revision is considered as alpha and will not be supported in future. The old setup will not be preserved. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: imx8mn: Reorder flexspi clock-names entryKuldeep Singh1-1/+1
Reorder flexspi clock-names entry to make it compliant with bindings. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: imx8mm: Reorder flexspi clock-names entryKuldeep Singh1-1/+1
Reorder flexspi clock-names entry to make it compliant with bindings. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: ls1028a: set up the real link speed for ENETC port 2Vladimir Oltean1-1/+1
In NXP LS1028A there is a MAC-to-MAC internal link between enetc_port2 and mscc_felix_port4. This link operates at 2.5Gbps and is described as such for the mscc_felix_port4 node. The reason for the discrepancy is a limitation in the PHY library support for fixed-link nodes. Due to the fact that the PHY library registers a software PHY which emulates the clause 22 register map, the drivers/net/phy/fixed_phy.c driver only supports speeds up to 1Gbps. The mscc_felix_port4 node is probed by DSA, which does not use the PHY library directly, but phylink, and phylink has a different representation for fixed-link nodes, one that does not have the limitation of not being able to represent speeds > 1Gbps. Since the enetc driver was converted to phylink too as of commit 71b77a7a27a3 ("enetc: Migrate to PHYLINK and PCS_LYNX"), the limitation has been practically lifted there too, and we can describe the real link speed in the device tree now. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: imx8mm-nitrogen-r2: add ecspi2 supportAdrien Grassein1-0/+20
Add the description for ecspi2 support. Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29arm64: dts: imx: add imx8qm mek supportDong Aisheng2-0/+145
The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53 proccessor with powerful graphic and multimedia features. This patch adds i.MX8QuadMax MEK board support. Note that MX8QM needs a special workaround for TLB flush due to a SoC errata, otherwise there may be random crash if enable both clusters of A72 and A53. As the errata workaround is still not in mainline, so we disable A72 cluster first for MX8QM MEK. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>