aboutsummaryrefslogtreecommitdiffstats
path: root/tools/perf/scripts/python/export-to-postgresql.py (unfollow)
AgeCommit message (Collapse)AuthorFilesLines
2021-10-26ARM: dts: arm: Update register-bit-led nodes 'reg' and node namesRob Herring9-57/+144
Add a 'reg' entry for register-bit-led nodes on the Arm Ltd platforms. The 'reg' entry is the LED control register address. With this, the node name can be updated to use a generic node name, 'led', and a unit-address. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20211024232003.211484-1-linus.walleij@linaro.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-22dts: socfpga: Add Mercury+ AA1 devicetreePaweł Anikiel2-0/+113
Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Signed-off-by: Joanna Brozek <jbrozek@antmicro.com> Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Maciej Mikunda <mmikunda@antmicro.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20211021151736.2096926-2-pan@semihalf.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-22ARM: dts: spear13xx: Drop malformed 'interrupt-map' on PCI nodesRob Herring2-8/+0
The spear13xx PCI 'interrupt-map' property is not parse-able. '#interrupt-cells' is missing and there are 3 #address-cells. Based on the driver, the only supported interrupt is for MSI. Therefore, 'interrupt-map' is not needed. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20211022141156.2592221-1-robh@kernel.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-21ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ceClaudiu Beznea1-0/+12
Use blocks 0 and 1 of TCB0 for clocksource and clockevent functionality. PIT64B is already enabled on SAMA7G5 targets for this but TCB0 will be used as a fallback only in case PIT64B will fail to probe. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211020094656.3343242-4-claudiu.beznea@microchip.com
2021-10-21ARM: dts: at91: sama7g5: add tcb nodesClaudiu Beznea1-0/+20
Add TCB nodes. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211020094656.3343242-3-claudiu.beznea@microchip.com
2021-10-21ARM: dts: at91: sama7g5: add rtc nodeEugen Hristev1-0/+7
Add RTC node. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> [claudiu.beznea: add sama7g5 compatible as the IP has 2 extra registers compared with sam9x60] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211020094656.3343242-2-claudiu.beznea@microchip.com
2021-10-21ARM: dts: aspeed: Add uart routing to device treeChia-Wei Wang3-0/+18
Add LPC uart routing to the device tree for Aspeed SoCs. Signed-off-by: Oskar Senft <osk@google.com> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Tested-by: Lei YU <yulei.sh@bytedance.com> Link: https://lore.kernel.org/r/20210927023053.6728-6-chiawei_wang@aspeedtech.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Enable earlyconJoel Stanley1-1/+1
Rainier was missed when enabling all of the other machines in commit 239566b032f3 ("ARM: dts: aspeed: Set earlycon boot argument"). Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Add front panel LEDsJoel Stanley1-0/+42
These were meant to be part of commit 4fb27b3f9176 ("ARM: dts: aspeed: rainier: Add system LEDs") but went missing. Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Add 'factory-reset-toggle' as GPIOF6Isaac Kurth1-1/+1
The state of this GPIO determines whether a factory reset has been requested. If a physical switch is used, it can be high or low. During boot, the software checks and records the state of this switch. If it is different than the previous recorded state, then the read-write portions of memory are reformatted. Signed-off-by: Isaac Kurth <isaac.kurth@ibm.com> Reviewed-by: Adriana Kobylak <anoo@us.ibm.com> Link: https://lore.kernel.org/r/20210714214741.1547052-1-blisaac91@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Remove PSU gpio-keysB. J. Wyman1-28/+0
Remove the gpio-keys entries for the power supply presence lines from the Rainier device tree. The user space applications are going to change from using libevdev to libgpiod. Signed-off-by: B. J. Wyman <bjwyman@gmail.com> Link: https://lore.kernel.org/r/20210623230401.3050076-1-bjwyman@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Remove gpio hog for GPIOP7Eddie James1-7/+0
Only the pass 1 Ingraham board (Rainier system) had a micro-controller wired to GPIOP7 on ball Y23. Pass 2 boards have this ball wired to the heartbeat LED, so remove the hog as this device tree supports pass 2. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20210915214738.34382-5-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Add eeprom on bus 12Eddie James1-0/+5
The devicetree was missing an eeprom. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20210915214738.34382-4-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: p10bmc: Enable KCS channel 2Andrew Jeffery2-0/+10
Rainier uses KCS channel 2 as the source for the debug-trigger application outlined at [1] and implemented at [2]. [1] https://github.com/openbmc/docs/blob/master/designs/bmc-service-failure-debug-and-recovery.md [2] https://github.com/openbmc/debug-trigger Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210623033854.587464-8-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: p10bmc: Use KCS 3 for MCTP bindingAndrew Jeffery2-5/+12
The MCTP LPC driver was loaded by hacking up the compatible in the devicetree node for KCS 4. With the introduction of the raw KCS driver this hack is no-longer required. Use the regular compatible string for KCS 4 and configure the appropriate SerIRQ. The reset state of the status bits on KCS 4 is inappropriate for the MCTP LPC binding. Switch to KCS 3 which has a different reset behaviour. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: Adding Inventec Transformers BMCLin.TommySC 林世欽 TAO2-0/+329
Initial introduction of Inventec Transformers x86 family equipped with AST2600 BMC SoC. Signed-off-by: Tommy Lin <Lin.TommySC@inventec.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/7d7b20575f994a3c9018223a3c5f198d@inventec.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: everest: Fix bus 15 muxed eepromsEddie James1-20/+20
The eeproms on bus 15 muxes were at the wrong addresses. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211020215321.33960-6-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: everest: Add IBM Operation Panel I2C deviceEddie James1-1/+7
Set I2C bus 14 to multi-master mode and add the panel device that will register the I2C controller as a slave device. In addition, in early Everest systems, the panel device was behind an I2C switch, which doesn't work for slave mode. Get it working (albeit unreliably, since a master transaction might switch the switch at any moment) by defaulting the switch channel to the one with the panel. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211020215321.33960-5-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: everest: Add I2C switch on bus 8Eddie James1-0/+23
The switch controls two busses containing some VRMs. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211020215321.33960-4-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier and everest: Remove PCA gpio specificationEddie James2-1181/+0
Specifying gpio nodes under PCA led controllers no longer does anything, so remove those nodes in the device trees. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211020215321.33960-3-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: p10bmc: Fix ADC iio-hwmon battery node nameEddie James2-2/+2
In keeping with previous systems, call the iio-hwmon bridge node "iio-hwmon-battery" to distinguish it as the battery voltage sensor. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211020215321.33960-2-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-20ARM: dts: mstar: Mark timer with arm,cpu-registers-not-fw-configuredRomain Perier1-0/+1
The vendor u-boot does not configure the arch timer correctly on MStar, let Linux do it. Signed-off-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Daniel Palmer <daniel@0x0f.com> Link: https://lore.kernel.org/linux-arm-kernel/20210923170747.5786-2-romain.perier@gmail.com
2021-10-20ARM: dts: mstar: Add rtc device nodeRomain Perier1-0/+8
This adds the definition of the rtc device node. The RTC being able to work with the oscillator at 12Mhz for now, it shares the same xtal than the watchdog. Signed-off-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Daniel Palmer <daniel@0x0f.com> Link: https://lore.kernel.org/all/20210823171613.18941-4-romain.perier@gmail.com
2021-10-20arm64: dts: rockchip: Add idle cooling devices to rk3399Daniel Lezcano1-0/+12
The thermal framework accepts now the cpu idle cooling device as an alternative when the cpufreq cooling device fails. Add the node in the DT so the cooling devices will be present and the platforms can extend the thermal zone definition to add them. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20211001161728.1729664-1-daniel.lezcano@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-20ARM: dts: rockchip: remove usb-phy fallback string from rk3066a/rk3188Johan Jonker2-4/+2
With the conversion of rockchip-usb-phy.yaml a long time used fallback string for rk3066a/rk3188 was added. The linux driver doesn't do much with the GRF phy address range, however the u-boot driver rockchip_usb2_phy.c does. The bits in GRF_UOC0_CON2 for rk3066a/rk3188 and rk3288 for example don't match. Remove the usb-phy fallback string for rk3066a/rk3188 to prevent possible strange side effects. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210828111218.10026-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-20ARM: dts: gemini: Consolidate PCI interrupt-map propertiesRob Herring6-91/+20
The Gemini PCI 'interrupt-map' does not vary by board, so let's move the definition to a common location. This avoids having incomplete interrupt properties (i.e. #interrupt-cells without interrupt-map). Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-20ARM: dts: ixp4xx: Group PCI interrupt properties togetherRob Herring13-2/+24
Move the PCI 'interrupt-map-mask' and '#interrupt-cells' properties alongside the 'interrupt-map' property in each board dts. This avoids having incomplete set of interrupt properties which may fail validation. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org>
2021-10-18arm64: dts: rockchip: fix resets in tsadc node for rk356xJohan Jonker1-2/+1
In the rockchip_thermal.c driver we now get the resets with a devm_reset_control_array_get() function, so remove the reset-names property as it is no longer needed. Although no longer required in rockchip-thermal.yaml sort tsadc-apb as first item. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210930110517.14323-4-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-17arm64: dts: rockchip: Add analog audio on Quartz64Nicolas Frattaroli1-3/+32
On the Quartz64 Model A, the I2S1 TDM controller is connected to the rk817 codec in I2S mode. Enabling it and adding the necessary simple-sound-card and codec nodes allows for analog audio output on the PINE64 Quartz64 Model A SBC. Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Link: https://lore.kernel.org/r/20211016105354.116513-5-frattaroli.nicolas@gmail.com [some property sorting] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-17arm64: dts: rockchip: Add i2s1 on rk356xNicolas Frattaroli1-0/+25
This adds the necessary device tree node on rk3566 and rk3568 to enable the I2S1 TDM audio controller. I2S0 has not been added, as it is connected to HDMI and there is no way to test that it's working without a functioning video clock (read: VOP2 driver). Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Link: https://lore.kernel.org/r/20211016105354.116513-4-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-17arm64: dts: rockchip: change gpio nodenamesJohan Jonker5-22/+22
Currently all gpio nodenames are sort of identical to there label. Nodenames should be of a generic type, so change them all. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211007144019.7461-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-17ARM: dts: rockchip: change gpio nodenamesJohan Jonker6-30/+30
Currently all gpio nodenames are sort of identical to there label. Nodenames should be of a generic type, so change them all. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211007144019.7461-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-16arm64: dts: rockchip: add 'chassis-type' propertyArnaud Ferraris4-0/+5
A new 'chassis-type' root node property has recently been approved for the device-tree specification, in order to provide a simple way for userspace to detect the device form factor and adjust their behavior accordingly. This patch fills in this property for end-user devices (such as laptops, smartphones and tablets) based on Rockchip ARM64 processors. Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com> Link: https://lore.kernel.org/r/20211016102025.23346-5-arnaud.ferraris@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-16arm64: dts: rockchip: add powerdomains to rk3368Heiko Stuebner1-0/+178
Add the core io-domain node for rk3368. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210925090405.2601792-3-heiko@sntech.de
2021-10-16dt-bindings: arm: rockchip: add rk3368 compatible string to pmu.yamlHeiko Stuebner1-0/+2
Add the compatible for the pmu mfd on rk3368. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210925090405.2601792-1-heiko@sntech.de
2021-10-16arm64: dts: rockchip: enable spdif on Quartz64 ANicolas Frattaroli1-0/+22
Add the necessary nodes to enable the spdif output on the RK3566-Quartz-A board. Co-developed-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Link: https://lore.kernel.org/r/20211015111303.1365328-2-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-16arm64: dts: rockchip: add spdif node to rk356xPeter Geis1-0/+14
This adds the spdif node to the rk356x device tree. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Link: https://lore.kernel.org/r/20211015111303.1365328-1-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-16arm64: dts: imx8mm-kontron: Add support for ultra high speed modes on SD cardFrieder Schrempf2-1/+29
In order to use ultra high speed modes (UHS) on the SD card slot, we add matching pinctrls and fix the voltage switching for LDO5 of the PMIC, by providing the SD_VSEL pin as GPIO to the PMIC driver. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-16arm64: dts: visconti: Add DTS for the VisROBO boardYuji Ishikawa3-0/+106
This board consists of two boards: the SoM board (VRC SoM) with the SoC on board, and the board for I/O (VRB). The functions of each board supported by this update are as follows: - VRC SoM - WDT - GPIO - SDCard (SPI-MMC mode) - I2C x1 - VRB board - VRC SoM - UART x2 - Ethernet phy Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp> Link: https://lore.kernel.org/r/20211014092703.15251-4-yuji2.ishikawa@toshiba.co.jp Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
2021-10-16dt-bindings: arm: toshiba: Add the TMPV7708 VisROBO VRB boardYuji Ishikawa1-0/+1
Add an entry for the Toshiba Visconti TMPV7708 VisROBO VRB board (tmpv7708-visrobo-vrb) to the board/SoC bindings. Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp> Link: https://lore.kernel.org/r/20211014092703.15251-3-yuji2.ishikawa@toshiba.co.jp Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
2021-10-16arm64: dts: visconti: Add 150MHz fixed clock to TMPV7708 SoCYuji Ishikawa1-0/+7
This clock source is referred by baudrate generators of SPI and I2C devices. Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp> Link: https://lore.kernel.org/r/20211014092703.15251-2-yuji2.ishikawa@toshiba.co.jp Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
2021-10-16arm64: dts: visconti: Add PCIe host controller support for TMPV7708 SoCNobuhiro Iwamatsu2-0/+58
Add PCIe node and fixed clock for PCIe in TMPV7708's dtsi, and tmpv7708-rm-mbrc boards's dts. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Link: https://lore.kernel.org/r/20210907042500.1525771-1-nobuhiro1.iwamatsu@toshiba.co.jp
2021-10-15ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151Amelie Delaunay1-1/+1
Referring to the note under USBH reset and clocks chapter of RM0436, "In order to access USBH_OHCI registers it is necessary to activate the USB clocks by enabling the PLL controlled by USBPHYC" (ck_usbo_48m). The point is, when USBPHYC PLL is not enabled, OHCI register access freezes the resume from STANDBY. It is the case when dual USBH is enabled, instead of OTG + single USBH. When OTG is probed, as ck_usbo_48m is USBO clock parent, then USBPHYC PLL is enabled and OHCI register access is OK. This patch adds ck_usbo_48m (provided by USBPHYC PLL) as clock of USBH OHCI, thus USBPHYC PLL will be enabled and OHCI register access will be OK. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-10-15ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15Olivier Moysan1-4/+4
Fix SAI2A and SAI2B pin muxings for AV96 board on STM32MP15. Change sai2a-4 & sai2a-5 to sai2a-2 & sai2a-2. Change sai2a-4 & sai2a-sleep-5 to sai2b-2 & sai2b-sleep-2 Fixes: dcf185ca8175 ("ARM: dts: stm32: Add alternate pinmux for SAI2 pins on stm32mp15") Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-10-15ARM: dts: stm32: fix SAI sub nodes register rangeOlivier Moysan1-8/+8
The STM32 SAI subblocks registers offsets are in the range 0x0004 (SAIx_CR1) to 0x0020 (SAIx_DR). The corresponding range length is 0x20 instead of 0x1c. Change reg property accordingly. Fixes: 5afd65c3a060 ("ARM: dts: stm32: add sai support on stm32mp157c") Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-10-15ARM: dts: stm32: fix STUSB1600 Type-C irq level on stm32mp15xx-dkxFabrice Gasnier1-1/+1
STUSB1600 IRQ (Alert pin) is active low (open drain). Interrupts may get lost currently, so fix the IRQ type. Fixes: 83686162c0eb ("ARM: dts: stm32: add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-10-15ARM: dts: stm32: set the DCMI pins on stm32mp157c-odysseyGrzegorz Szymaszek1-0/+6
The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output. The DCMI pins used on this output are defined in the pin state definition &pinctrl/dcmi-1, AKA &dcmi_pins_b (added in mainline commit 02814a41529a55dbfb9fbb2a3728e78e70646ea6). Set these pins as the default pinctrl of the DCMI peripheral in the board device tree. The pins are not used for any other purpose, so it seems safe to assume most users will not need to override (delete) what this patch provides. status defaults to "disabled", so the peripheral will not be unnecessarily started. And the users who actually intend to make use of a camera on the DVP port will have this little part of the configuration ready. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-10-15ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHzMarek Vasut1-1/+1
The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM, which causes additional signal delay. At 108 MHz, this delay triggers a sporadic issue where the first bit of RX data is not received by the QSPI controller. There are two options of addressing this problem, either by using the DLYB block to compensate the extra delay, or by reducing the QSPI bus clock frequency. The former requires calibration and that is overly complex, so opt for the second option. Fixes: 76045bc457104 ("ARM: dts: stm32: Add QSPI NOR on AV96") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-10-15ARM: dts: stm32: add initial support of stm32mp135f-dk boardAlexandre Torgue3-0/+121
Add support of stm32mp135f discovery board (part number: STM32MP135F-DK). It embeds a STM32MP135F SOC with 512 MB of DDR3. Several connections are available on this board: 4*USB2.0, 1*USB2.0 typeC DRD, SDcard, 2*RJ45, HDMI, Combo Wifi/BT, ... Only SD card, uart4 (console) and watchdog IPs are enabled in this commit. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2021-10-15dt-bindings: stm32: document stm32mp135f-dk boardAlexandre Torgue1-0/+4
Add new entry for stm32mp135f-dk board. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Rob Herring <robh@kernel.org>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.