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2016-12-21clk: renesas: mstp: Support 8-bit registers for r7s72100Chris Brandt1-5/+22
The RZ/A1 is different than the other Renesas SOCs because the MSTP registers are 8-bit instead of 32-bit and if you try writing values as 32-bit nothing happens...meaning this driver never worked for r7s72100. Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi") Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-12clk: bcm: Fix 'maybe-uninitialized' warning in bcm2835_clock_choose_div_and_prate()Boris Brezillon1-1/+1
best_rate is reported as potentially uninitialized by gcc. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Fixes: 155e8b3b0ee3 ("clk: bcm: Support rate change propagation on bcm2835 clocks") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: add devm_get_clk_from_child() APIKuninori Morimoto2-4/+46
Some driver is using this type of DT bindings for clock (more detail, see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt). sound_soc { ... cpu { clocks = <&xxx>; ... }; codec { clocks = <&xxx>; ... }; }; Current driver in this case uses of_clk_get() for each node, but there is no devm_of_clk_get() today. OTOH, the problem of having devm_of_clk_get() is that it encourages the use of of_clk_get() when clk_get() is more desirable. Thus, this patch adds new devm_get_clk_from_chile() which explicitly reads as get a clock from a child node of this device. By this function, we can also use this type of DT bindings sound_soc { clocks = <&xxx>, <&xxx>; clock-names = "cpu", "codec"; clock-ranges; ... cpu { ... }; codec { ... }; }; Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [sboyd@codeurora.org: Rename subject to clk + add API] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: st: clk-flexgen: Unmap region obtained by of_iomapArvind Yadav1-1/+4
Free memory mapping, if probe is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: keystone: pll: Unmap region obtained by of_iomapArvind Yadav1-2/+7
Free memory mapping, if of_pll_div_clk_init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk:mmp:clk-of-mmp2: Free memory and Unmap region obtained by kzalloc and of_iomapArvind Yadav1-3/+12
Free memory and memory mapping , if mmp2_clk_init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> [sboyd@codeaurora.org: Put return at the right place] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk:mmp:clk-of-pxa910: Free memory and Unmap region obtained by kzmalloc and of_iomapArvind Yadav1-4/+15
Free memory and memory mapping , if pxa910_clk_init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: mmp: clk-of-pxa1928: Free memory obtained by kzallocArvind Yadav1-0/+3
Free memory, if init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: cdce925: Fix limit checkChristophe JAILLET1-1/+1
It is likely that instead of '1>64', 'q>64' was expected. Moreover, according to datasheet, http://www.ti.com/lit/ds/symlink/cdce925.pdf SCAS847I - JULY 2007 - REVISED OCTOBER 2016 PLL settings limits are: 16 <= q <= 63 So change the upper limit check from 64 to 63. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: bcm: Make COMMON_CLK_IPROC into a libraryStephen Boyd1-11/+5
The broadcom clk driver Kconfig file selects and depends on the COMMON_CLK_IPROC config for different SoC specific drivers. Let's simplify this by always selecting the COMMON_CLK_IPROC config, turning it into a set of library code. We still want to retain the SoC specific options, so we leave those in place. Since we're here we also drop COMMON_CLK dependency because that's implicitly handled by including this file in drivers/clk/Kconfig in the right place and also make CLK_BCM_KONA default to y on the architecture it exists for instead of plain default y. Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Ray Jui <ray.jui@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: qoriq: added ls1012a clock configurationTang Yuantian1-0/+19
Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [sboyd@codeaurora.org: Sorted list] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: ti: dra7: fix "failed to lookup clock node gmac_gmii_ref_clk_div" boot messageGrygorii Strashko1-1/+0
Prevent creating clk alias for non existing gmac_gmii_ref_clk_div clock and, this way, eliminate excessive error message during boot: "ti_dt_clocks_register: failed to lookup clock node gmac_gmii_ref_clk_div" Fixes: c097338ebd3f ("ARM: dts: dra7: cpsw: fix clocks tree") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clockBoris Brezillon1-1/+6
The VEC clock requires needs to be set at exactly 108MHz. Allow rate change propagation on PLLH_AUX to match this requirement wihtout impacting other IPs (PLLH is currently only used by the HDMI encoder, which cannot be enabled when the VEC encoder is enabled). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: bcm: Support rate change propagation on bcm2835 clocksBoris Brezillon1-4/+63
Some peripheral clocks, like the VEC (Video EnCoder) clock need to be set to a precise rate (in our case 108MHz). With the current implementation, where peripheral clocks are not allowed to forward rate change requests to their parents, it is impossible to match this requirement unless the bootloader has configured things correctly, or a specific rate has been assigned through the DT (with the assigned-clk-rates property). Add a new field to struct bcm2835_clock_data to specify which parent clocks accept rate change propagation, and support set rate propagation in bcm2835_clock_determine_rate(). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clkBoris Brezillon1-1/+3
bcm2835_pll_divider_off() is resetting the divider field in the A2W reg to zero when disabling the clock. Make sure we preserve this value by reading the previous a2w_reg value first and ORing the result with A2W_PLL_CHANNEL_DISABLE. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Cc: <stable@vger.kernel.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: ti: omap36xx: Work around sprz319 advisory 2.1Richard Watts4-11/+104
The OMAP36xx DPLL5, driving EHCI USB, can be subject to a long-term frequency drift. The frequency drift magnitude depends on the VCO update rate, which is inversely proportional to the PLL divider. The kernel DPLL configuration code results in a high value for the divider, leading to a long term drift high enough to cause USB transmission errors. In the worst case the USB PHY's ULPI interface can stop responding, breaking USB operation completely. This manifests itself on the Beagleboard xM by the LAN9514 reporting 'Cannot enable port 2. Maybe the cable is bad?' in the kernel log. Errata sprz319 advisory 2.1 documents PLL values that minimize the drift. Use them automatically when DPLL5 is used for USB operation, which we detect based on the requested clock rate. The clock framework will still compute the PLL parameters and resulting rate as usual, but the PLL M and N values will then be overridden. This can result in the effective clock rate being slightly different than the rate cached by the clock framework, but won't cause any adverse effect to USB operation. Signed-off-by: Richard Watts <rrw@kynesim.co.uk> [Upported from v3.2 to v4.9] Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-07clk: clk-wm831x: fix a logic errorPan Bian1-1/+1
Fix bug https://bugzilla.kernel.org/show_bug.cgi?id=188561. Function wm831x_clkout_is_prepared() returns "true" when it fails to read CLOCK_CONTROL_1. "true" means the device is already prepared. So return "true" on the read failure seems improper. Signed-off-by: Pan Bian <bianpan2016@163.com> Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Fixes: f05259a6ffa4 ("clk: wm831x: Add initial WM831x clock driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-07clk: uniphier: add cpufreq data for LD11, LD20 SoCsMasahiro Yamada2-1/+61
Add more data to 64bit SoCs for the cpufreq support. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-07clk: uniphier: add CPU-gear change (cpufreq) supportMasahiro Yamada4-2/+136
Core support code for CPU frequency changes, which will be used by the generic cpufreq driver. The register view is different from the generic clk-mux; it has a separate status register, and an update bit to load the register setting. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: Put venus core0/1 gdscs to hw control modeSricharan R1-0/+2
The venus video ip's internal core blocks are under the control of the firmware and their powerdomains needs to be 'ON' only when used by the firmware. So putting it into hw controlled mode lets this to happen, otherwise the firmware hangs checking for this. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: gdsc: Add support for gdscs with HW controlRajendra Nayak2-0/+19
Some GDSCs might support a HW control mode, where in the power domain (gdsc) is brought in and out of low power state (while unsued) without any SW assistance, saving power. Such GDSCs can be configured in a HW control mode when powered on until they are explicitly requested to be powered off by software. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: bcm: Fix unmet Kconfig dependencies for CLK_BCM_63XXFlorian Fainelli1-1/+1
With commit f4e871509959 ("clk: iproc: Make clocks visible options"), COMMON_CLK_IPROC gained a dependency on ARCH_BCM_IPROC, yet CLK_BCM_63XX also selects that option, this causes the following Kconfig warning: warning: (CLK_BCM_63XX) selects COMMON_CLK_IPROC which has unmet direct dependencies ((ARCH_BCM_IPROC || COMPILE_TEST) && COMMON_CLK) Fix this by adding proper depends for COMMON_CLK_IPROC Fixes: f4e871509959 ("clk: iproc: Make clocks visible options") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> [sboyd@codeaurora.org: Drop default part as it's redundant] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clockIcenowy Zheng1-1/+1
In the user manual of A33 SoC, the bit 22 and 23 of pll-mipi control register is called "LDO{1,2}_EN", and according to the BSP source code from Allwinner [1], the LDOs are enabled during the clock's enabling process. The clock failed to generate output if the two LDOs are not enabled. Add the two bits to the clock's gate bits, so that the LDOs are enabled when the PLL is enabled. [1] https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L429 Fixes: d05c748bd730 ("clk: sunxi-ng: Add A33 CCU support") Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-11-23clk: bcm2835: Fix ->fixed_divider of pllh_auxBoris Brezillon1-1/+1
There is no fixed divider on pllh_aux. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: clk-rpm: Fix clk_hw referencesGeorgi Djakov1-14/+22
Fix the clk_hw references to the actual clocks and add a xlate function to return the hw pointers from the already existing static array. Reported-by: Michael Scott <michael.scott@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: clk-smd-rpm: Fix clk_hw referencesGeorgi Djakov1-14/+22
Fix the clk_hw references to the actual clocks and add a xlate function to return the hw pointers from the already existing static array. Reported-by: Michael Scott <michael.scott@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_opsRajendra Nayak5-18/+18
The sdcc driver for msm8996/msm8916/msm8974/msm8994 and apq8084 expects a clk_set_rate() on the sdcc rcg clk to set a floor value of supported clk rate closest to the requested rate, by looking up the frequency table. So move all the sdcc rcgs on all these platforms to use the newly introduced clk_rcg2_floor_ops Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: Add rcg ops to return floor value closest to the requested rateRajendra Nayak4-9/+86
The default behaviour with clk_rcg2_ops is for the clk_round_rate()/clk_set_rate() to return/set a ceil clock rate closest to the requested rate by looking up the corresponding frequency table. However, we do have some instances (mainly sdcc on various platforms) of clients expecting a clk_set_rate() to set a floor value instead. Add a new clk_rcg2_floor_ops to handle this for such specific rcg instances Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-21clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating itChen-Yu Tsai1-1/+1
The PLL-MIPI clock is somewhat special as it has its own LDOs which need to be turned on for this PLL to actually work and output a clock signal. Add the 2 LDO enable bits to the gate bits. This fixes issues with the TCON not sending vblank interrupts when the tcon and dot clock are indirectly clocked from the PLL-MIPI clock. Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-11-18clk: exynos5433: Mark some clocks as criticalMarek Szyprowski1-14/+14
Some parent clocks of the Exynos5433 CMUs must be always enabled to access any register in the given CMU or devices connected to it. For the time being, until a proper solution based on runtime PM is applied, mark those clocks as critical (instead of ignore unused) to prevent disabling them. Reported-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-11-17clk: exynos5433: Add documentation for the audio block parent clocksMarek Szyprowski1-0/+7
Audio block requires access to two parent clocks: audio PLL and oscillator, so add this information to device tree bindings documentation. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-11-17clk: exynos5433: Fix parent clocks for FSYS blockMarek Szyprowski2-4/+4
The proper parent clock for FSYS block is "aclk_fsys_200" according to the Exynos5433 reference manual. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-11-16clk: sunxi-ng: Mark structs static and cleanup spacesStephen Boyd1-6/+6
Some checkpatch warnings about spaces were missed and we didn't mark two structs as static. Clean it up. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-16clk: efm32gg: Pass correct type to hw provider registrationStephen Boyd1-1/+1
Dan Carpenter reports that we're passing a pointer to a pointer here when we should just be passing a pointer. Pass the right pointer so that the of_clk_hw_onecell_get() sees the appropriate data pointer on its end. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Cc: Stephen Boyd <stephen.boyd@linaro.org> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Fixes: 9337631f52a8 ("clk: efm32gg: Migrate to clk_hw based OF and registration APIs") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-16clk: berlin: Pass correct type to hw provider registrationStephen Boyd2-2/+2
Dan Carpenter reports that we're passing a pointer to a pointer here when we should just be passing a pointer. Pass the right pointer so that the of_clk_hw_onecell_get() sees the appropriate data pointer on its end. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Cc: Jisheng Zhang <jszhang@marvell.com> Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Stephen Boyd <stephen.boyd@linaro.org> Fixes: f6475e298297 ("clk: berlin: Migrate to clk_hw based registration and OF APIs") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-16clk: rockchip: add clock controller for rk1108Shawn Lin3-0/+547
Add the clock tree definition and driver for rk1108 SoC. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Jacob Chen <jacob2.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>