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2021-02-24PCI: dwc: Don't assume the ops in dw_pcie always existJisheng Zhang3-13/+11
Some dwc-based device drivers, especially host-only drivers, may work well with the default read_dbi/write_dbi/link_up implementations in pcie-designware.c, so remove the assumption that every driver implements them to simplify those drivers. Link: https://lore.kernel.org/r/20210128144258.10329aa4@xhacker.debian Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-24PCI: dwc: Add upper limit address for outbound iATUShradha Todi2-0/+6
The size parameter is unsigned long type which can accept size > 4GB. In that case, the upper limit address must be programmed. Add support to program the upper limit address and set INCREASE_REGION_SIZE in case size > 4GB. Link: https://lore.kernel.org/r/1612250918-19610-1-git-send-email-shradha.t@samsung.com Signed-off-by: Shradha Todi <shradha.t@samsung.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Rob Herring <robh@kernel.org>
2021-02-24PCI: dwc: Change size to u64 for EP outbound iATUShradha Todi2-2/+2
Since outbound iATU permits size to be greater than 4GB for which the support is also available, allow EP function to send u64 size instead of truncating to u32. Link: https://lore.kernel.org/r/1609929900-19082-1-git-send-email-shradha.t@samsung.com Signed-off-by: Shradha Todi <shradha.t@samsung.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
2021-02-24PCI: dwc: Drop support for config space in 'ranges'Rob Herring1-33/+12
Since commit a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code"), the code setting dbi_base when the config space is defined in 'ranges' property instead of 'reg' is dead code as dbi_base is never NULL. Rather than fix this, let's just drop the code. Using ranges has been deprecated since 2014. The only platforms using this were exynos5440, i.MX6 and Spear13xx. Exynos5440 is dead and has been removed. i.MX6 and Spear13xx had PCIe support added just before this was deprecated and were fixed within a kernel release or 2. Link: https://lore.kernel.org/r/20201215194149.86831-1-robh@kernel.org Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-24PCI: layerscape: Convert to builtin_platform_driver()Michael Walle1-2/+3
fw_devlink will defer the probe until all suppliers are ready. We can't use builtin_platform_driver_probe() because it doesn't retry after probe deferral. Convert it to builtin_platform_driver(). Link: https://lore.kernel.org/r/20210120105246.23218-1-michael@walle.cc Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-24PCI: layerscape: Add LX2160A rev2 EP mode supportHou Zhiqiang1-0/+7
The LX2160A rev2 uses the same PCIe IP as LS2088A, but LX2160A rev2 PCIe controller is integrated with different stride between PFs' register address. Link: https://lore.kernel.org/r/20201026051448.1913-2-Zhiqiang.Hou@nxp.com Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-24dt-bindings: PCI: layerscape: Add LX2160A rev2 compatible stringsHou Zhiqiang1-0/+1
Add PCIe Endpoint mode compatible string "fsl,lx2160ar2-pcie-ep" Link: https://lore.kernel.org/r/20201026051448.1913-1-Zhiqiang.Hou@nxp.com Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
2021-02-24PCI: dwc: Work around ECRC configuration issueVidya Sagar2-2/+48
DesignWare core has a TLP digest (TD) override bit in one of the control registers of ATU. This bit also needs to be programmed for proper ECRC functionality. This is currently identified as an issue with DesignWare IP version 4.90a. [bhelgaas: fix typos/grammar errors] Link: https://lore.kernel.org/r/20201230165723.673-1-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI/portdrv: Report reset for frozen channelKeith Busch1-1/+2
The PCI error recovery always resets the link for a frozen state, so the port driver should return that a reset is required for its result. This will get the .slot_reset() callback invoked, which is necessary to restore the port's config space. Without this, the driver had been relying on downstream drivers to return this status. Link: https://lore.kernel.org/r/20210104230300.1277180-6-kbusch@kernel.org Tested-by: Hedi Berriche <hedi.berriche@hpe.com> Signed-off-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Hedi Berriche <hedi.berriche@hpe.com>
2021-02-23PCI/AER: Specify the type of Port that was resetKeith Busch1-1/+2
The AER driver may be called upon to reset either a Downstream or a Root Port. Check which type it is to properly identify it when logging that the reset occurred. Link: https://lore.kernel.org/r/20210104230300.1277180-5-kbusch@kernel.org Tested-by: Hedi Berriche <hedi.berriche@hpe.com> Signed-off-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Hedi Berriche <hedi.berriche@hpe.com>
2021-02-23PCI/ERR: Retain status from error notificationKeith Busch1-2/+1
Overwriting the frozen detected status with the result of the link reset loses the NEED_RESET result that drivers are depending on for error handling to report the .slot_reset() callback. Retain this status so that subsequent error handling has the correct flow. Link: https://lore.kernel.org/r/20210104230300.1277180-4-kbusch@kernel.org Reported-by: Hinko Kocevar <hinko.kocevar@ess.eu> Tested-by: Hedi Berriche <hedi.berriche@hpe.com> Signed-off-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sean V Kelley <sean.v.kelley@intel.com> Acked-by: Hedi Berriche <hedi.berriche@hpe.com>
2021-02-23PCI/AER: Clear AER status from Root Port when resetting Downstream PortKeith Busch1-1/+1
The pci_dev parameter given to aer_root_reset() may be a Downstream Port rather than the Root Port. Get the Root Port from the provided device in order to clear the root's AER status. Link: https://lore.kernel.org/r/20210104230300.1277180-3-kbusch@kernel.org Tested-by: Hedi Berriche <hedi.berriche@hpe.com> Signed-off-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sean V Kelley <sean.v.kelley@intel.com> Acked-by: Hedi Berriche <hedi.berriche@hpe.com>
2021-02-23PCI/ERR: Clear status of the reporting deviceKeith Busch1-7/+6
Error handling operates on the first Downstream Port above the detected error, but the error may have been reported by a downstream device. Clear the AER status of the device that reported the error rather than the first Downstream Port. Link: https://lore.kernel.org/r/20210104230300.1277180-2-kbusch@kernel.org Tested-by: Hedi Berriche <hedi.berriche@hpe.com> Signed-off-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sean V Kelley <sean.v.kelley@intel.com> Acked-by: Hedi Berriche <hedi.berriche@hpe.com>
2021-02-23MAINTAINERS: Add Daire McNamara as Microchip PCIe driver maintainerDaire McNamara1-0/+7
Link: https://lore.kernel.org/r/20210125162934.5335-5-daire.mcnamara@microchip.com Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI: microchip: Add Microchip PolarFire PCIe controller driverDaire McNamara3-0/+1149
Add support for the Microchip PolarFire PCIe controller when configured in host (Root Complex) mode. [bhelgaas: wrap lines to fit in 80 columns, fix trivial style issues] Link: https://lore.kernel.org/r/20210125162934.5335-4-daire.mcnamara@microchip.com Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> [lorenzo.pieralisi@arm.com: minor comments tweak] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org>