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2019-10-01soc: renesas: Add Renesas R8A774B1 config optionBiju Das1-0/+6
Add configuration option for the RZ/G2N (R8A774B1) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1567675844-19247-4-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-01soc: renesas: r8a77990-sysc: Fix power request conflictsGeert Uytterhoeven1-0/+3
Describe the location and contents of the SYSCEXTMASK register on R-Car E3, to prevent conflicts between internal and external power requests. Based on a patch in the BSP by Dien Pham <dien.pham.ry@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190828113618.6672-8-geert+renesas@glider.be
2019-10-01soc: renesas: r8a77980-sysc: Fix power request conflictsGeert Uytterhoeven1-0/+3
Describe the location and contents of the SYSCEXTMASK register on R-Car V3H, to prevent conflicts between internal and external power requests. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190828113618.6672-7-geert+renesas@glider.be
2019-10-01soc: renesas: r8a77970-sysc: Fix power request conflictsGeert Uytterhoeven1-0/+3
Describe the location and contents of the SYSCEXTMASK register on R-Car V3M, to prevent conflicts between internal and external power requests. Based on a patch in the BSP by Dien Pham <dien.pham.ry@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190828113618.6672-6-geert+renesas@glider.be
2019-10-01soc: renesas: r8a77965-sysc: Fix power request conflictsGeert Uytterhoeven1-0/+3
Describe the location and contents of the SYSCEXTMASK register on R-Car M3-N, to prevent conflicts between internal and external power requests. Based on a patch in the BSP by Dien Pham <dien.pham.ry@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190828113618.6672-5-geert+renesas@glider.be
2019-10-01soc: renesas: r8a7796-sysc: Fix power request conflictsGeert Uytterhoeven2-2/+22
Describe the location and contents of the SYSCEXTMASK register on R-Car M3-W, to prevent conflicts between internal and external power requests. This register does not exist on R-Car M3-W ES1.x. Based on a patch in the BSP by Dien Pham <dien.pham.ry@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190828113618.6672-4-geert+renesas@glider.be
2019-10-01soc: renesas: r8a7795-sysc: Fix power request conflictsGeert Uytterhoeven2-6/+28
Describe the location and contents of the SYSCEXTMASK register on R-Car H3, to prevent conflicts between internal and external power requests. This register does not exist on R-Car H3 ES1.x and ES2.x. Based on a patch in the BSP by Dien Pham <dien.pham.ry@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190828113618.6672-3-geert+renesas@glider.be
2019-10-01soc: renesas: rcar-sysc: Prepare for fixing power request conflictsGeert Uytterhoeven2-0/+19
Recent R-Car Gen3 SoCs added an External Request Mask Register to the System Controller (SYSC). This register allows to mask external power requests for CPU or 3DG domains, to prevent conflicts between powering off CPU cores or the 3D Graphics Engine, and changing the state of another power domain through SYSC, which could lead to CPG state machine lock-ups. Add support for making use of this register. Take into account that the register is optional, and that its location and contents are SoC-specific. Note that the issue fixed by this cannot happen in the upstream kernel, as upstream has no support for graphics acceleration yet. SoCs lacking the External Request Mask Register may need a different mitigation in the future. Inspired by a patch in the BSP by Dien Pham <dien.pham.ry@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190828113618.6672-2-geert+renesas@glider.be