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2022-02-25arm64: dts: renesas: r8a779f0: Add pinctrl device nodeGeert Uytterhoeven1-0/+6
Add a device node for the Pin Function Controller on the Renesas R-Car S4-8 (R8A779F0) SoC. Note that the register block does not include registers for banks 4-7, as they can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/cf4d261ba1253879e117f1598b9f47798cbda635.1645458249.git.geert+renesas@glider.be
2022-02-25ARM: dts: at91: sama7g5: add oppsClaudiu Beznea1-0/+38
Add OPPs for SAMA7G5 along with clock for CPU. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-9-claudiu.beznea@microchip.com
2022-02-25ARM: dts: at91: sama7g5ek: set regulator voltages for standby stateClaudiu Beznea1-0/+5
Set regulator voltages for standby state to avoid wrong behavior of system while in standby. The CPU voltage has been chosen as being the one corresponding to OPP=600MHz. Next commit will set the 600MHz OPP as the suspend OPP. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-8-claudiu.beznea@microchip.com
2022-02-25ARM: dts: at91: fix low limit for CPU regulatorClaudiu Beznea1-1/+1
Fix low limit for CPU regulator. Otherwise setting voltages lower than 1.125V will not be allowed (CPUFreq will not be allowed to set proper voltages on proper frequencies). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-7-claudiu.beznea@microchip.com
2022-02-25ARM: dts: at91: sama7g5: Enable can0 and can1 support in sama7g5-ekHari Prasath1-0/+25
Enable the can0 and can1 controllers in sama7g5-ek board along with its pin mux settings. Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220222113924.25799-3-Hari.PrasathGE@microchip.com
2022-02-25ARM: dts: at91: sama7g5: Add can controllers of sama7g5Hari Prasath1-0/+96
Add support for all the six CAN controllers of sama7g5.The internal SRAM of 128KB is split among the CAN controllers for the message RAM elements leaving a small portion reserved for power management. The SRAM split up is as below. Lower 64K: PM 13K can-0 17K can-1 17K can-2 17K Higher 64K: can-3 17K can-4 17K can-5 17K Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220222113924.25799-2-Hari.PrasathGE@microchip.com
2022-02-25ARM: dts: at91: sama7g5: Add crypto nodesTudor Ambarus1-0/+32
Describe and enable the AES, SHA and TDES crypto IPs. Tested with the extra run-time self tests of the registered crypto algorithms. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220208105646.226623-1-tudor.ambarus@microchip.com
2022-02-24ARM: dts: at91: Use the generic "crypto" node name for the crypto IPsTudor Ambarus4-12/+12
The DT specification recommeds that: "The name of a node should be somewhat generic, reflecting the function of the device and not its precise programming model. If appropriate, the name should be one of the following choices:" "crypto" being the recommendation for the crypto nodes. Follow the DT recommendation and use the generic "crypto" node name for the at91 crypto IPs. While at this, add labels to the crypto nodes where they missed, for easier reference purposes. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220208111225.234685-1-tudor.ambarus@microchip.com
2022-02-24ARM: dts: at91: remove status = "okay" from soc specific dtsiClaudiu Beznea4-13/+0
Remove status = "okay" from SoC specific dtsi as this is the default state. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220207111523.575474-1-claudiu.beznea@microchip.com
2022-02-24ARM: dts: at91: sama5d2: Fix PMERRLOC resource sizeTudor Ambarus1-1/+1
PMERRLOC resource size was set to 0x100, which resulted in HSMC_ERRLOCx register being truncated to offset x = 21, causing error correction to fail if more than 22 bit errors and if 24 or 32 bit error correction was supported. Fixes: d9c41bf30cf8 ("ARM: dts: at91: Declare EBI/NAND controllers") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: <stable@vger.kernel.org> # 4.13.x Acked-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220111132301.906712-1-tudor.ambarus@microchip.com
2022-02-24dt-bindings: arm: at91: add Kontron's new KSwitchesMichael Walle1-0/+9
The Kontron KSwitch D10 MMT series ethernet switches features a LAN9668 SoC with either 8 copper ports or 6 copper port and two SFP cages. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220210131817.484922-1-michael@walle.cc
2022-02-24MAINTAINERS: Update Allwinner SoCs maintainersJernej Skrabec1-2/+2
Maxime is stepping down as a maintainer, I'll take more active role and Samuel joined the team. Maxime, thank you for your effort! Samuel, welcome! Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Samuel Holland <samuel@sholland.org> Acked-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20220220210714.2484019-1-jernej.skrabec@gmail.com
2022-02-24ARM: dts: add DT for lan966 SoC and 2-port board pcb8291Kavyasree Kotagiri3-0/+303
This patch adds basic DT for Microchip lan966x SoC and associated board pcb8291(2-port EVB). Adds peripherals required to allow booting: Interrupt Controller, Clock, Generic ARMv7 Timers, Synopsys Timer, Flexcoms, GPIOs. Also adds other peripherals like crypto(AES/SHA), DMA, Watchdog Timer, TRNG and MCAN0. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220221080858.14233-1-kavyasree.kotagiri@microchip.com
2022-02-24ARM: dts: renesas: Align GPIO hog names with dtschemaGeert Uytterhoeven6-8/+8
Dtschema expects GPIO hogs to end with a "hog" suffix. Also, the convention for node names is to use hyphens, not underscores. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/972d982024cbb04dcf29b2a0ac6beaf41e66c363.1645705927.git.geert+renesas@glider.be
2022-02-24arm64: dts: renesas: Align GPIO hog names with dtschemaGeert Uytterhoeven7-9/+9
Dtschema expects GPIO hogs to end with a "hog" suffix. Also, the convention for node names is to use hyphens, not underscores. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/baee4b9980576ffbab24122fce7147c9cbc2ea59.1645705998.git.geert+renesas@glider.be
2022-02-24arm64: dts: renesas: rzg2lc-smarc-som: Enable watchdogBiju Das1-0/+14
Enable watchdog{0, 1, 2} interfaces on RZ/G2LC SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220223165813.24833-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-24ARM: dts: r9a06g032-rzn1d400-db: Enable watchdog0 with a 60s timeoutJean-Jacques Hiblot1-0/+5
60s is a sensible default value. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Link: https://lore.kernel.org/r/20220221095032.95054-5-jjhiblot@traphandler.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-24ARM: dts: r9a06g032: Add the watchdog nodesJean-Jacques Hiblot1-0/+16
This SoC includes 2 watchdog controllers (one per A7 core). Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Link: https://lore.kernel.org/r/20220221095032.95054-4-jjhiblot@traphandler.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-24dt-bindings: clock: r9a06g032: Add the definition of the watchdog clockJean-Jacques Hiblot1-0/+1
This clock is actually the REF_SYNC_D8 clock. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220221095032.95054-2-jjhiblot@traphandler.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-24arm64: dts: rockchip: align Google CROS EC PWM node name with dtschemaKrzysztof Kozlowski1-1/+1
dtschema expects PWM node name to be a generic "pwm". This also matches Devicetree specification requirements about generic node names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20220214081916.162014-5-krzysztof.kozlowski@canonical.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-24arm64: dts: rockchip: enable rk809 audio codec on the rk3568 evb1-v10Michael Riesch1-1/+30
Enable the Rockchip RK809 audio codec on the Rockchip RK3568 EVB1-V10. This requires the VCCIO_ACODEC voltage regulator to be set to always on. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220222175004.1308990-2-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-24arm64: dts: rockchip: set vdd_gpu regulator on rk3568-evb1-v10 to always onMichael Riesch1-0/+1
As discussed in [0], the Rockchip power domain driver does not consider the external supplies (such as VDD_GPU on the RK3568 EVB1). In the scope of this discussion it has been pointed out that turning this voltage on/off on the fly is not explicitly supported. This patch follows the other RK356x boards by example and sets the vdd_gpu regulator to always on. [0] https://lore.kernel.org/linux-rockchip/20211217130919.3035788-1-s.hauer@pengutronix.de/ Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220223112008.1316132-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-24arm64: dts: rockchip: add the vdd_cpu regulator to rk3568-evb1-v10Michael Riesch1-0/+33
The TCS4525 voltage regulator provides the vdd_cpu on the Rockchip RK3568 EVB1. Add the device tree node and connect it to the CPU nodes. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220223162054.1626257-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-24arm64: dts: rockchip: enable work led on rk3568-evb1-v10Michael Riesch1-0/+20
Enable the blue work LED on the Rockchip RK3568 EVB1-V10. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220222175004.1308990-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-22arm64: dts: renesas: spider-cpu: Enable watchdog timerGeert Uytterhoeven1-0/+5
Enable the watchdog timer on the Spider board. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/b36b2bb5770e10d906571721a3d73ca205b6f56e.1642525158.git.geert+renesas@glider.be
2022-02-22arm64: dts: renesas: r8a779f0: Add RWDT nodeGeert Uytterhoeven1-0/+10
Add a device node for the RCLK Watchdog Timer (RWDT) on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/556a7f41bdadceecbe8b59b79ac7e9f592ca17a2.1642525158.git.geert+renesas@glider.be
2022-02-22ARM: dts: imx6qp-sabresd: Enable PCIe supportRichard Zhu1-1/+5
In the i.MX6QP sabresd board(sch-28857) design, one external oscillator is powered up by vgen3 and used as the PCIe reference clock source by the endpoint device. If RC uses this oscillator as reference clock too, PLL6(ENET PLL) would has to be in bypass mode, and ENET clocks would be messed up. To keep things simple, let RC use the internal PLL as reference clock and set vgen3 always on to enable the external oscillator for endpoint device on i.MX6QP sabresd board. NOTE: This reference clock setup is used to pass the GEN2 TX compliance tests, and isn't recommended as a setup in the end-user design. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: juno: Add separate SCMI variantsRobin Murphy5-1/+255
While Juno's SCP firmware initially spoke the SCPI protocol, binary releases since 2018, and the newer open-source codebase, only speak SCMI and thus aren't particularly compatibile with the DTs we currently have upstream. Add a parallel set of variant DTs for boards with up-to-date firmware, replacing the SCPI parts with their new SCMI equivalents. Link: https://lore.kernel.org/r/f3516815104f951a05fc0f799681f77d7968f6ac.1645125063.git.robin.murphy@arm.com Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-02-21MAINTAINERS: Specify IRC channel for Renesas ARM64 portSergey Shtylyov1-0/+1
The Renesas ARM ports do have their own IRC channel #renesas-soc (initially created on Freenode, then moved to Liberta.Chat). Hopefully, adding it to this file will attract more people... :-) Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Link: https://lore.kernel.org/r/6c08e98f-c7bb-9d95-5032-69022e43e39b@omp.ru Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-21MAINTAINERS: Specify IRC channel for Renesas ARM32 portSergey Shtylyov1-0/+1
The Renesas ARM ports do have their own IRC channel #renesas-soc (initially created on Freenode, then moved to Liberta.Chat). Hopefully, adding it to this file will attract more people... :-) Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Link: https://lore.kernel.org/r/2f108f63-0cf7-cc4c-462e-ec63736234cf@omp.ru Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-21arm64: dts: renesas: ulcb-kf: fix wrong commentNikita Yushchenko1-1/+1
Fix comment referencing salvator board, likely a copy-paste leftover. ulcb-kf.dtsi has nothing to do with salvator. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Fixes: 80c07701d5918928 ("arm64: dts: renesas: ulcb-kf: add pcm3168 sound codec") Link: https://lore.kernel.org/r/20220216181003.114049-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-21arm64: dts: meson: add support for OSMC Vero 4K+Christian Hewitt2-0/+118
The OSMC Vero 4K+ device is based on the Amlogic S905D (P230) reference design with the following specifications: - 2GB DDR4 RAM - 16GB eMMC - HDMI 2.1 video - S/PDIF optical output - AV output - 10/100/1000 Ethernet - AP6255 Wireless (802.11 a/b/g/n/ac, BT 4.2) - 2x USB 2.0 ports (1x OTG) - IR receiver (internal) - IR extender port (external) - 1x micro SD card slot - 1x Power LED (red) - 1x Reset button (in AV jack) Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Tested-by: Chad Wagner <wagnerch42@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220211105311.30320-4-christianshewitt@gmail.com
2022-02-21dt-bindings: arm: amlogic: add Vero 4K+ bindingsChristian Hewitt1-0/+1
Add the board binding for the OSMC Vero 4K+ STB device Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220211105311.30320-3-christianshewitt@gmail.com
2022-02-21dt-bindings: vendor-prefixes: add osmc prefixChristian Hewitt1-0/+2
Open Source Media Centre (Sam Nazarko Trading Ltd.) are a manufacturer of Linux Set-Top Box devices. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220211105311.30320-2-christianshewitt@gmail.com
2022-02-21arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMCJonas Kuenstler1-0/+2
Set the usdhc root clock to 400MHz to be able to support HS400/HS400ES modes for eMMC on phyCORE-i.MX8MP SoM. Signed-off-by: Jonas Kuenstler <j.kuenstler@phytec.de> Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of LDO4Teresa Remmet1-2/+2
LDO4 is not connected so disable it. And LDO5 is used for VSEL of the NVCC_SD2 SD-Card bus. Having it disabled seems not to have an impact on the functionality. We enable it, as it is used. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltageTeresa Remmet1-0/+2
Add bindings for VDD_ARM (BUCK2) run and standby voltage. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Update WDOG muxingTeresa Remmet1-1/+1
To be able to trigger a reset also from an external source we need to configure the WDOG pin as open drain. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx linesTeresa Remmet1-6/+6
Reduce drive strength on fec tx lines for signal quality improvements. Measurements showed that TD0 and TD1 require X4 and the other lines X2 for optimized settings. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strengthTeresa Remmet1-8/+8
Set eMMC drive strength for USDHC3_DATA lines (200Mhz) to X4 for signal improvement. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth phyTeresa Remmet1-0/+1
To fit spec requirements set minimum output impedance for dp83867 ethernet phy. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlay for imx219 rpi v2 cameraTim Harvey2-0/+95
Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module: - https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf - has its own on-board 24MHz osc so no clock required from baseboard - pin 11 enables 1.8V and 2.8V LDO which is connected to GW73xx MIPI_GPIO4 (IMX8MM GPIO1_IO1) so we use this as a gpio Support is added via a device-tree overlay. The IMX219 supports RAW8/RAW10 image formats. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlay for imx219 rpi v2 cameraTim Harvey2-0/+95
Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module: - https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf - has its own on-board 24MHz osc so no clock required from baseboard - pin 11 enables 1.8V and 2.8V LDO which is connected to GW73xx MIPI_GPIO4 (IMX8MM GPIO1_IO1) so we use this as a gpio controlled regulator enable. Support is added via a device-tree overlay. The IMX219 supports RAW8/RAW10 image formats. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlays for serial modesTim Harvey4-0/+181
The imx8mm-venice-gw72xx-0x som+baseboard combination has a multi-protocol RS-232/RS-485/RS-422 transceiver to an off-board connector which can be configured in a number of ways via UART and GPIO configuration. The default configuration per the imx8mm-venice-gw72xx-0x dts is for UART2 TX/RX and UART4 TX/RX to be available as RS-232: J15.1 UART2 TX out J15.2 UART2 RX in J15.3 UART4 TX out J15.4 UART4 RX in J15.5 GND Add dt overlays to allow additional the modes of operation: rs232-rts (UART2 RS-232 with RTS/CTS hardware flow control) J15.1 TX out J15.2 RX in J15.3 RTS out J15.4 CTS in J15.5 GND rs485 (UART2 RS-485 half duplex) J15.1 TXRX- J15.2 N/C J15.3 TXRX+ J15.4 N/C J15.5 GND rs422 (UART2 RS-422 full duplex) J15.1 TX- J15.2 RX+ J15.3 TX+ J15.4 RX- J15.5 GND Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlays for serial modesTim Harvey4-0/+183
The imx8mm-venice-gw73xx-0x som+baseboard combination has a multi-protocol RS-232/RS-485/RS-422 transceiver to an off-board connector which can be configured in a number of ways via UART and GPIO configuration. The default configuration per the imx8mm-venice-gw73xx-0x dts is for UART2 TX/RX and UART4 TX/RX to be available as RS-232: J15.1 UART2 TX out J15.2 UART2 RX in J15.3 UART4 TX out J15.4 UART4 RX in J15.5 GND Add dt overlays to allow additional the modes of operation: rs232-rts (UART2 RS-232 with RTS/CTS hardware flow control) J15.1 TX out J15.2 RX in J15.3 RTS out J15.4 CTS in J15.5 GND rs485 (UART2 RS-485 half duplex) J15.1 TXRX- J15.2 N/C J15.3 TXRX+ J15.4 N/C J15.5 GND rs422 (UART2 RS-422 full duplex) J15.1 TX- J15.2 RX+ J15.3 TX+ J15.4 RX- J15.5 GND Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21dt-bindings: arm: imx: add imx8mm gw7903 supportTim Harvey1-0/+1
The GW7903 is based on the i.MX 8M Mini SoC featuring: - LPDDR4 DRAM - eMMC FLASH - microSD connector with UHS support - LIS2DE12 3-axis accelerometer - Gateworks System Controller - IMX8M FEC - software selectable RS232/RS485/RS422 serial transceiver - PMIC - 2x off-board bi-directional opto-isolated digital I/O - 1x M.2 A-E Key Socket and 1x MiniPCIe socket with USB2.0 and PCIe (resistor loading to route PCIe/USB2 between M.2 and MiniPCIe socket) Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx: Add i.mx8mm Gateworks gw7903 dts supportTim Harvey2-0/+837
The GW7903 is based on the i.MX 8M Mini SoC featuring: - LPDDR4 DRAM - eMMC FLASH - microSD connector with UHS support - LIS2DE12 3-axis accelerometer - Gateworks System Controller - IMX8M FEC - software selectable RS232/RS485/RS422 serial transceiver - PMIC - 2x off-board bi-directional opto-isolated digital I/O - 1x M.2 A-E Key Socket and 1x MiniPCIe socket with USB2.0 and PCIe (resistor loading to route PCIe/USB2 between M.2 and MiniPCIe socket) Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: ls1028a: add efuse nodeMichael Walle1-0/+11
Layerscape SoCs contain a Security Fuse Processor which is basically a efuse controller. Add the node, so userspace can read the efuses. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-evk: add support for I2C5Hugo Villeneuve1-0/+22
Add support for i2c5, which is used to access the external I2C bus on connector J22 of the imx8mp-evk. Limit the speed to 100kHz since this is an external I2C bus. Disabled by default, since it is shared with the CAN1 bus. To enable i2c5, you need to disable the CAN1 function, enable the i2c5 function and also configure the CAN1/I2C5_SEL GPIO to HIGH to select i2c5 instead of CAN1. This can be done by defining a gpio-hog inside the pca6416 node, in your board device tree, like in this example: &flexcan1 { status = "disabled"; }; &i2c5 { status = "okay"; }; &pca6416 { can1-i2c5-sel-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; output-high; line-name = "can1-i2c5-sel"; }; }; Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-evk: add PCA6416 gpio line namesHugo Villeneuve1-0/+16
Add gpio-line-names for the various GPIO's connected to the PCA6416 I/O expander on the imx8mp EVK. This helps when using the new gpiod interface to find the GPIOs by name. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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