aboutsummaryrefslogtreecommitdiffstats
path: root/tools/perf/scripts/python/export-to-postgresql.py (unfollow)
AgeCommit message (Collapse)AuthorFilesLines
2018-08-01mmc: tmio: Fix tuning flowMasaharu Hayakawa1-2/+0
If the return value of mmc_send_tuning() is error other than -EILSEQ, the tuning fails and process goes out of for_loop. The correct processing is to judge their TAP as not good (NG) and continue. Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> [Niklas: update commit message] Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-08-01mmc: sunxi: remove output of virtual base addressAndre Przywara1-1/+4
Recent Linux versions refuse to print actual virtual kernel addresses, to not give a hint about the location of the kernel in a randomized virtual address space. This affects the output of the sunxi MMC controller driver, which now produces the rather uninformative line: [ 1.482660] sunxi-mmc 1c0f000.mmc: base:0x(____ptrval____) irq:8 Since the virtual base address is not really interesting in the first place, let's just drop this value. The same applies to Linux' notion of the interrupt number, which is independent from the GIC SPI number. We have the physical address as part of the DT node name, which is way more useful for debugging purposes. To keep a success message in the driver, we make this purpose explicit with the word "initialized", plus print some information that is not too obvious and that we learned while probing the device: the maximum request size and whether it uses the new timing mode. So the output turns into: [ 1.750626] sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB, uses new timings mode [ 1.786699] sunxi-mmc 1c11000.mmc: initialized, max. request size: 2048 KB Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-08-01dt-bindings: mmc: rockchip-dw-mshc: add description for px30Liang Chen1-0/+1
Add "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc" for dwmmc on px30 platform. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-08-01mmc: renesas_sdhi: Add r8a77990 supportWolfram Sang1-0/+1
This patch adds SDHI support for the R8A77990 SoC (R-Car E3). No driver changes needed for anything except HS400 which we will enable separately later. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-08-01mmc: sunxi: allow 3.3V DDR when DDR is availableIcenowy Zheng1-1/+1
Some Allwinner boards feature an on-board eMMC with fixed 3.3V voltage (e.g. Banana Pi M2+), and in this case both the eMMC and the SoC are capable of doing 3.3V DDR transmission. Add capability of 3.3V DDR when DDR is available (extra clock or new timing). Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-08-01mmc: mmci: Add and implement a ->dma_setup() callback for qcom dmlUlf Hansson4-11/+20
As a first step to improve the variant specific code for mmci, add a ->dma_setup() callback to the struct mmci_host_ops. To show its use, let's deploy the callback for the qcom dml, which involves also to the assign the mmci_host_ops pointer from the variant ->init() callback. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Ludovic Barre <ludovic.barre@st.com>
2018-07-30mmc: mmci: Initial support to manage variant specific callbacksUlf Hansson2-73/+82
To be able to better support different mmci variants, we need to be able to use variant specific callbacks, rather than continue to sprinkle the code with additional variant data. To move in this direction, let's add an optional ->init() callback to the variant data struct, which variants shall use to assign the mmci_host_ops pointer. Using an ->init() callback enables us to partition the code between different files. To allow separate mmci variant files to implement the variant specifics, let's also move the definition of the struct variant_data to the common mmci header file. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Ludovic Barre <ludovic.barre@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-30mmc: tegra: Force correct divider calculation on DDR50/52Aapo Vienamo1-1/+16
Tegra SDHCI controllers require the SDHCI clock divider to be configured to divide the clock by two in DDR50/52 modes. Incorrectly configured clock divider results in corrupted data. Prevent the possibility of incorrectly calculating the divider value due to clock rate rounding or low parent clock frequency by not assigning host->max_clk to clk_get_rate() on tegra_sdhci_set_clock(). See the comments for further details. Fixes: a8e326a ("mmc: tegra: implement module external clock change") Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-30mmc: sdhci: Add MSI interrupt support for O2 SD hosternest.zhang1-0/+25
Add MSI interrupt support if the SD host device can support MSI interrupt. Signed-off-by: ernest.zhang <ernest.zhang@bayhubtech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-30mmc: sdhci: Add support for O2 hardware tuningernest.zhang2-1/+84
Add hardware tuning function instead of software tuning because O2/Bayhub SD host controller support hardware tuning. Signed-off-by: ernest.zhang <ernest.zhang@bayhubtech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-30mmc: sdhci: Export sdhci tuning function symbolernest.zhang2-4/+13
Export sdhci tuning function symbols which are used by other SD Host controller driver modules. Signed-off-by: ernest.zhang <ernest.zhang@bayhubtech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-30mmc: sdhci: Change O2 Host HS200 mode clock frequency to 200MHzernest.zhang1-3/+2
O2 SD Host HS200 mode clock frequency current is 208MHz, should be changed to 200MHz to meet specification. Signed-off-by: ernest.zhang <ernest.zhang@bayhubtech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-30mmc: sdhci: Add support for O2 eMMC HS200 modeernest.zhang1-0/+18
When use eMMC as boot device, the eMMC signaling voltage is tied to 1.8v fixed output voltage, bios can set o2 sd host controller PCI configuration register 0x308 bit4 to 1 to let driver skip 3.3v signaling voltage and direct use 1.8v singling voltage in eMMC initialize process. Signed-off-by: ernest.zhang <ernest.zhang@bayhubtech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: tegra: Add and use tegra_sdhci_get_max_clock()Aapo Vienamo1-2/+9
Implement and use tegra_sdhci_get_max_clock() which returns the true maximum host clock rate. The issue with tegra_sdhci_get_max_clock() is that it returns the current clock rate of the host instead of the maximum one, which can lead to unnecessarily small clock rates. This differs from the previous implementation of tegra_sdhci_get_max_clock() in that it doesn't divide the result by two. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: mxcmmc: Fix missing parentheses and braceKees Cook1-1/+2
Looks like the adjusted syntax wasn't fully build tested. This fixes failures with powerpc builds: drivers/mmc/host/mxcmmc.c: In function ‘mxcmci_swap_buffers’: drivers/mmc/host/mxcmmc.c:296:51: error: expected ‘)’ before ‘;’ token void *buf = kmap_atomic(sg_page(sg) + sg->offset; ^ drivers/mmc/host/mxcmmc.c:299:1: error: expected ‘,’ or ‘;’ before ‘}’ token } ^ Fixes: b189e7589f6d3 ("mmc: mxcmmc: handle highmem pages") Signed-off-by: Kees Cook <keescook@chromium.org> Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: sdhci-esdhc-imx: fix indentStefan Agner1-1/+1
Fix indent. This also makes disable/enable clock blocks look alike. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: sdhci-esdhc-imx: disable clocks before changing frequencyStefan Agner1-6/+6
In the uSDHC case (e.g. i.MX 6) clocks only get disabled if frequency is set to 0. However, it could be that the stack asks for a frequency change while clocks are on. In that case the function clears the divider registers (by clearing ESDHC_CLOCK_MASK) while the clock is enabled! This causes a short period of time where the clock is undivided (on a i.MX 6DL a clock of 196MHz has been measured). For older IP variants the driver disables clock by clearing some bits in ESDHC_SYSTEM_CONTROL. Make sure to disable card clock before changing frequency for uSDHC IP variants too. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: tegra: prevent ACMD23 on Tegra 3Stefan Agner1-1/+9
It seems that SD3.0 advertisement needs to be set for higher eMMC speed modes (namely DDR52) as well. The TRM states that the SD3.0 advertisement bit should be set for all controller instances, even for those not supporting UHS-I mode... When specifying vqmmc-supply as a fixed 1.8V regulator on a Tegra SD/MMC instance which is connected to a eMMC device, the stack enables SD3.0. However, enabling it has consequences: If SDHCI 3.0 support is advertised the stack enables Auto-CMD23. Unfortunately Auto-CMD23 seems not to work well with Tegra 3 currently. It leads to regular warnings: mmc2: Got command interrupt 0x00010000 even though no command operation was in progress. It is not entirely clear why those errors happens. It seems that a Linux 3.1 based downstream kernel which has Auto-CMD23 support does not show those warnings. Use quirk SDHCI_QUIRK2_ACMD23_BROKEN to prevent Auto-CMD23 being used for now. With this the eMMC works stable on high-speed mode while still announcing SD3.0. This allows to use mmc-ddr-1_8v to enables DDR52 mode. In DDR52 mode read speed improves from about 42MiB/s to 72MiB/s on an Apalis T30. Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: tegra: fix eMMC DDR52 modeStefan Agner1-1/+2
Make sure the clock is doubled when using eMMC DDR52 mode. Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: tegra: prevent HS200 on Tegra 3Stefan Agner1-1/+2
The stack assumes that SDHC controller which support SD3.0 (SDR104) do support HS200. This is not the case for Tegra 3, which does support SD 3.0 but only supports eMMC spec 4.41. Use SDHCI_QUIRK2_BROKEN_HS200 to indicate that the controller does not support HS200. Note that commit 156e14b126ff ("mmc: sdhci: fix caps2 for HS200") added the tie between SD3.0 (SDR104) and HS200. I don't think that this is necessarly true. It is fully legitimate to support SD3.0 and not support HS200. The quirk naming suggests something is broken in the controller, but this is not the case: The controller simply does not support HS200. Fixes: 7ad2ed1dfcbe ("mmc: tegra: enable UHS-I modes") Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: sdhci-pci-dwc-mshc: synopsys dwc mshc supportPrabu Thangamuthu5-1/+97
Synopsys has DWC MSHC controller on HPAS-DX platform connected using PCIe interface with SD card slot and eMMC device slots. This patch is to enable SD cards connected on this platform. As Clock generation logic is implemented using MMCM module of HAPS-DX platform, we have separate functions to control the MMCM to generate required clocks with respect to speed mode. Signed-off-by: Prabu Thangamuthu <prabu.t@synopsys.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: sdhci-esdhc-imx: Switch to SPDX identifierFabio Estevam1-4/+1
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: sdhci-of-dwcmshc: add SDHCI OF Synopsys DWC MSHC driverJisheng Zhang3-0/+128
Add a driver for SDHCI OF Synopsys DesignWare Cores Mobile Storage Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com>