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2021-08-14dt-bindings: vendor-prefixes: add Traverse TechnologiesMathew McBride1-0/+2
Traverse Technologies is a designer and manufacturer of networking appliances. Signed-off-by: Mathew McBride <matt@traverse.com.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: add device tree for Traverse Ten64 (LS1088A)Mathew McBride2-0/+390
The Traverse Technologies Ten64 is a Mini-ITX form factor networking board using the NXP LS1088A SoC. This device tree only describes features which the mainline kernel currently has support for, such as some I2C-connected devices that are not described at present. System documentation may be found at ten64doc.traverse.com.au Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> # for the MAC/PHY Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: ls1088a: add missing PMU nodeMathew McBride1-0/+5
The Performance Manager Unit was not described in the DTS which meant performance event monitoring was not possible. This was exposed by a change to the PMU handling in KVM in 5.11-rc3 which now prevents a PMU being exposed to a guest when the host does not provide one: "KVM: arm64: Don't access PMCR_EL0 when no PMU is available" Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: ls1088a: add internal PCS for DPMAC1 nodeMathew McBride1-0/+13
A previous patch added the PCS for DPMAC2 only, as used for the AQR PHY on the LS1088ARDB. DPMAC1 PCS access is required for PHYLINK SFP support on the Traverse Ten64 board. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14dt-bindings: arm: fsl: add SKOV imx6q and imx6dl based boardsOleksij Rempel1-0/+5
Add SKOV imx6q/dl LT2, LT6 and mi1010ait-1cp1 boards. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14dt-bindings: vendor-prefixes: Add an entry for SKOV A/SOleksij Rempel1-0/+2
Add "skov" entry for the SKOV A/S: https://www.skov.com/en/ Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mq-reform2: add sound supportLucas Stach1-0/+49
This adds sound support to the Reform2. It differs from the downstream implementation in that the codec is used as the BCLK and FSYNC master and the i.MX8MQ only supplies a fixed 25MHz MCLK from the oscillator. This allows to support a wider range of audio rates by using the codec PLL and to shut down the audio PLLs on the i.MX8MQ SoC side. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8m: drop interrupt-affinity for pmuPeng Fan4-4/+0
i.MX8M use PPI for pmu, interrupt-affinity is not needed. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8qxp: update pmu compatiblePeng Fan1-1/+1
i.MX8QXP features four Cortex-A35 cores, use more accurate compatible. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm: update pmu compatiblePeng Fan1-1/+1
i.MX8MM features four Cortex-A53 cores, update the compatible to use more accurate "arm,cortex-a53-pmu" Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: ls1046a: fix eeprom entriesRaag Jadav2-13/+2
ls1046afrwy and ls1046ardb boards have CAT24C04[1] and CAT24C05[2] eeproms respectively. Both are 4Kb (512 bytes) in size, and compatible with AT24C04[3]. Remove multi-address entries, as both the boards have a single chip each. [1] https://www.onsemi.com/pdf/datasheet/cat24c01-d.pdf [2] https://www.onsemi.com/pdf/datasheet/cat24c03-d.pdf [3] https://ww1.microchip.com/downloads/en/DeviceDoc/doc0180.pdf Signed-off-by: Raag Jadav <raagjadav@gmail.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm-venice-gw7901: enable pull-down on gpio outputsTim Harvey1-3/+3
Enable internal pull-down on UART transceiver GPIO config pins. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm-venice-gw7901: add support for USB hub subloadTim Harvey1-3/+4
The USB hub has it's reset as GPIO4_IO17 but can be sub-loaded and VBUS provided by a VBUS regulator with GPIO4_IO2 as the enable and GPIO1_IO15 as the active-low over-current. Enable pull-up for GPIO4_IO17 to keep hub out of reset and move VBUS enable to GPIO4_IO2. Additionally enable pull-up on GPIO1_IO15 so that if the hub is loaded it never over-currents. This allows USB to work in both configurations without a device-tree change. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm-venice-gw71xx: fix USB OTG VBUSTim Harvey1-2/+3
The GW71xx has a USB Type-C connector with USB 2.0 signaling. GPIO1_12 is the power-enable to the TPS25821 Source controller and power switch responsible for monitoring the CC pins and enabling VBUS. Therefore GPIO1_12 must always be enabled and the vbus output enable from the IMX8MM can be ignored. To fix USB OTG VBUS enable a pull-up on GPIO1_12 to always power the TPS25821 and change the regulator output to GPIO1_10 which is unconnected. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm-venice-gw700x: fix invalid pmic pin configTim Harvey1-8/+0
The GW700x PMIC does not have an interrupt. Remove the invalid pin config. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm-venice-gw700x: fix mp5416 pmic configTim Harvey1-19/+37
Fix various MP5416 PMIC configurations: - Update regulator names per dt-bindings - ensure values fit among valid register values - add required regulator-max-microamp property - add regulator-always-on prop Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mq: add mipi csi phy and csi bridge descriptionsMartin Kepplinger1-0/+104
Describe the 2 available CSI interfaces on the i.MX8MQ with the MIPI-CSI2 receiver (new driver) and the CSI Bridge that provides the user buffers (existing driver). An image sensor is to be connected to the MIPIs' second port, to be described in board files. Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx: Add i.mx8mm/imx8mn Gateworks gw7902 dts supportTim Harvey3-0/+1797
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring: - LPDDR4 DRAM - eMMC FLASH - Gateworks System Controller - LTE CAT M1 modem - USB 2.0 HUB - M.2 Socket with USB2.0, PCIe, and dual-SIM - IMX8M FEC - PCIe based GbE - RS232/RS485/RS422 serial transceiver - GPS - CAN bus - WiFi / Bluetooth - MIPI header (DSI/CSI/GPIO/PWM/I2S) - PMIC Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mp: Add dsp nodeDaniel Baluta1-0/+30
i.MX8 MPlus SoC integrates Cadence HIFI4 DSP. This core runs either a custom firmware or the open source SOF firmware [1] DSP device is handled by SOF OF driver found in sound/soc/sof/sof-of-dev.c Notice that the DSP node makes use of: - dsp_reserved, a reserved memory region for various Audio resources (e.g firmware loading, audio buffers, etc). - Messaging Unit (mu2) for passing notifications betweem ARM core and DSP. [1] https://thesofproject.github.io/latest/platforms/index.html Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8m: Replace deprecated fsl,usbphy DT props with physMarek Vasut2-3/+6
The fsl,usbphy DT property is deprecated, replace it with phys DT property and specify #phy-cells. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mq-evk: Remove unnecessary blank linesKwon Tae-young1-2/+0
Unnecessary blank lines do NOT help readability, so remove them. Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mq-evk: add CD pinctrl for usdhc2Kwon Tae-young1-3/+9
Add CD pinctrl for usdhc2. Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm-venice-gw7901: Remove unnecessary #address-cells/#size-cellsFabio Estevam1-2/+0
The following dtc build warning is seen with W=1: arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts:291.14-397.4: Warning (avoid_unnecessary_addr_size): /soc@0/bus@30800000/i2c@30a20000/gsc@20: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Remove the unnecessary #address-cells/#size-cells to fix it. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-By: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8: Add jpeg encoder/decoder nodesMirela Rabulea5-0/+109
Add dts for imaging subsytem, include jpeg nodes here. Tested on imx8qxp/qm. Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8qxp-ai_ml: Fix checkpatch warningsKwon Tae-young1-1/+1
Fix the following warnings reported by checkpatch: arch/..../imx8qxp-ai_ml.dts:198: WARNING: please, no space before tabs Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: ls1088ardb: update PHY nodes with IRQ informationIoana Ciornei1-0/+9
Describe the IRQs for both the QSGMII PHYs and the 10GBASE-R PHY found on the LS1088ARDB board. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: ls2088ardb: update PHY nodes with IRQ informationIoana Ciornei1-0/+4
Update the DTS nodes corresponding to the 4 10GBASE-R PHYs to describe their IRQ lines. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: lx2160ardb: update PHY nodes with IRQ informationIoana Ciornei1-0/+4
Update the DTS nodes for both the AR8035 and the AQR107 PHYs in order to describe their IRQ lines. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-13arm64: tegra: Fix compatible string for Tegra132 CPUsThierry Reding1-2/+2
The documented compatible string for the CPUs found on Tegra132 is "nvidia,tegra132-denver", rather than the previously used compatible string "nvidia,denver". Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: tamonten: Fix UART pad settingAndreas Obergschwandtner1-7/+7
This patch fixes the tristate and pullup configuration for UART 1 to 3 on the Tamonten SOM. Signed-off-by: Andreas Obergschwandtner <andreas.obergschwandtner@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: nexus7: Improve thermal zonesDmitry Osipenko1-4/+52
Use skin temperature for maintaining temperature that is suitable specifically for Nexus 7. Add CPU thermal zone that protects silicon. All these changes don't make a significant difference, but it is a more correct definition of thermal zones. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: acer-a500: Improve thermal zonesDmitry Osipenko1-9/+46
Use skin temperature for maintaining temperature that is suitable specifically for A500. Add CPU thermal zone that protects silicon. All these changes don't make a significant difference, but it is a more correct definition of thermal zones. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: acer-a500: Use verbose variant of atmel,wakeup-method valueDmitry Osipenko1-1/+2
The verbose variant of the atmel,wakeup-method value was lost when patch that added the property was merged because it conflicted with other patch, re-add it for consistency. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: acer-a500: Add power supplies to accelerometerDmitry Osipenko1-0/+3
Add power supplies to accelerometer node, for completeness. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: acer-a500: Remove bogus USB VBUS regulatorsDmitry Osipenko1-24/+1
The configuration of USB VBUS regulators was borrowed from downstream kernel, which is incorrect because the corresponding GPIOs are connected to PROX_EN (A501 3G model) and LED_EN pins in accordance to the board schematics. USB works fine with both GPIOs being disabled, so remove the bogus USB VBUS regulators. The USB VBUS of USB3 is supplied from the fixed 5v system regulator and device-mode USB1 doesn't have VBUS switches. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: jetson-tk1: Correct interrupt trigger type of temperature sensorDmitry Osipenko1-1/+1
The LM90 temperature sensor should use edge-triggered interrupt because LM90 hardware doesn't deassert interrupt line until temperature is back to normal state, which results in interrupt storm. Correct the interrupt trigger type. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: dalmore: Correct interrupt trigger type of temperature sensorDmitry Osipenko1-1/+1
The LM90 temperature sensor should use edge-triggered interrupt because LM90 hardware doesn't deassert interrupt line until temperature is back to normal state, which results in interrupt storm. Correct the interrupt trigger type. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: cardhu: Correct interrupt trigger type of temperature sensorDmitry Osipenko1-1/+1
The LM90 temperature sensor should use edge-triggered interrupt because LM90 hardware doesn't deassert interrupt line until temperature is back to normal state, which results in interrupt storm. Correct the interrupt trigger type. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: apalis: Correct interrupt trigger type of temperature sensorDmitry Osipenko2-2/+2
The LM90 temperature sensor should use edge-triggered interrupt because LM90 hardware doesn't deassert interrupt line until temperature is back to normal state, which results in interrupt storm. Correct the interrupt trigger type. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: nyan: Correct interrupt trigger type of temperature sensorDmitry Osipenko1-1/+1
The LM90 temperature sensor should use edge-triggered interrupt because LM90 hardware doesn't deassert interrupt line until temperature is back to normal state, which results in interrupt storm. Correct the interrupt trigger type. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: acer-a500: Add interrupt to temperature sensor nodeDmitry Osipenko1-0/+4
The TEMP_ALERT pin of LM90 temperature sensor is connected to Tegra SoC. Add interrupt property to the temperature sensor for completeness. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: nexus7: Add interrupt to temperature sensor nodeDmitry Osipenko1-0/+4
The TEMP_ALERT pin of LM90 temperature sensor is connected to Tegra SoC. Add interrupt property to the temperature sensor for completeness. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: paz00: Add interrupt to temperature sensor nodeDmitry Osipenko1-0/+4
The TEMP_ALERT pin of LM90 temperature sensor is connected to Tegra SoC. Add interrupt property to the temperature sensor for completeness. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: ouya: Add interrupt to temperature sensor nodeDmitry Osipenko1-7/+6
The TEMP_ALERT pin of LM90 temperature sensor is connected to Tegra SoC. Add interrupt property to the temperature sensor and enable it in pinmux, for completeness. Tested-by: Matt Merhar <mattmerhar@protonmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: Add SoC thermal sensor to Tegra30 device-treesDmitry Osipenko1-4/+83
Add the on-chip SoC thermal sensor to Tegra30 device-trees. Now CPU temperature reporting and thermal throttling is available on all Tegra30 devices universally. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-12arm64: tegra: Add missing interconnects property for USB on Tegra186Thierry Reding1-0/+3
The device tree node for the XUDC (USB device mode controller) is missing the interconnects property that describes the path to memory for the controller. Add the property so that the things like the DMA mask can be set by the operating system. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-12arm64: tegra: Add NVIDIA Jetson TX2 NX Developer Kit supportThierry Reding2-0/+719
The Jetson TX2 NX Developer Kit is very similar to the Jetson Nano, but uses the more powerful Tegra186 SoC. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-12arm64: tegra: Add PWM nodes on Tegra186Thierry Reding1-0/+88
These PWMs can be used for fan or LED backlight control. Add the device tree nodes for all existing controllers found on Tegra186 SoCs. None of these are enabled by default, which is left for the board DTS files to do when necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-12dt-bindings: tegra: Document NVIDIA Jetson TX2 NX developer kitThierry Reding1-0/+1
The Jetson TX2 NX Developer Kit is the same form factor as Jetson Nano, but uses the more powerful Tegra186 SoC for added performance. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-12dt-bindings: i2c: renesas,riic: Make interrupt-names requiredGeert Uytterhoeven1-0/+1
Now the I2C device nodes in all DTS files have gained "interrupt-names" properties, the "interrupt-names" property can be made required. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/da8d1973dcd419d8d9c8c662ee614952f3a6969e.1626267422.git.geert+renesas@glider.be
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