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2020-09-28phy: qcom-qmp: Add support for DP in USB3+DP combo phyStephen Boyd2-90/+775
Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy driver. We already have support for the USB3 part of the combo phy, so most additions are for the DP phy. Split up the qcom_qmp_phy{enable,disable}() functions into the phy init, power on, power off, and exit functions that the common phy framework expects so that the DP phy can add even more phy ops like phy_calibrate() and phy_configure(). This allows us to initialize the DP PHY and configure the AUX channel before powering on the PHY at the link rate that was negotiated during link training. The general design is as follows: 1) DP controller calls phy_init() to initialize the PHY and configure the dp_com register region. 2) DP controller calls phy_configure() to tune the link rate and voltage swing and pre-emphasis settings. 3) DP controller calls phy_power_on() to enable the PLL and power on the phy. 4) DP controller calls phy_configure() again to tune the voltage swing and pre-emphasis settings determind during link training. 5) DP controller calls phy_calibrate() some number of times to change the aux settings if the aux channel times out during link training. 6) DP controller calls phy_power_off() if the link rate is to be changed and goes back to step 2 to try again at a different link rate. 5) DP controller calls phy_power_off() and then phy_exit() to power down the PHY when it is done. The DP PHY contains a PLL that is different from the one used for the USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk output from the DP PLL after going through various dividers. Introduce clk ops for these two clks that just tell the child clks what the frequency of the pixel and link are. When the phy link rate is configured we call clk_set_rate() to update the child clks in the display clk controller on what rate is in use. The clk frequencies always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or 8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or HBR3) so we simply store the link rate and use that to calculate the clk frequencies. The PLL enable sequence is a little different from other QMP phy PLLs so we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called from phy_power_on(). This should probably be split out better so that each phy has a way to run the final PLL/PHY enable sequence. This code is based on a submission of this phy and PLL in the drm subsystem. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org Link: https://lore.kernel.org/r/20200916231202.3637932-8-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Use devm_platform_ioremap_resource() to simplifyStephen Boyd1-8/+3
We can use the wrapper API here to save some lines and remove the need for the 'base' and 'res' local variable. Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-7-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Get dp_com I/O resource by indexStephen Boyd1-7/+3
The dp_com resource is always at index 1 according to the dts files in the kernel. Get this resource by index so that we don't need to make future additions to the DT binding use 'reg-names'. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-6-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy'Stephen Boyd1-57/+56
The serdes I/O region is where the PLL for the phy is controlled. Sometimes the PLL is shared between multiple phys, for example in the PCIe case where there are three phys inside the same wrapper. Other times the PLL is for a single phy, i.e. some USB3 phys. To complete the trifecta we have the USB3+DP combo phy where the USB3 and DP phys each have their own serdes region because they have their own PLL while they both share a common I/O region pertaining to the USB type-c pinout and cable orientation. Let's move the serdes iomem pointer into 'struct qmp_phy' so that we can correlate PLL control to the phy that uses it. This allows us to support the USB3+DP combo phy in this driver. This isn't a problem for the 3-lane/phy PCIe phy because there is a common init function that is the only place the serdes region is programmed. Furthermore, move the configuration data that contains most of the register programming sequences to the qmp phy struct. This data isn't qmp wrapper specific. It is phy specific data used to tune various settings for things like pre-emphasis, bias, etc. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-5-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Remove 'initialized' in favor of 'init_count'Stephen Boyd1-7/+2
We already track if any phy inside the qmp wrapper has been initialized by means of the struct qcom_qmp::init_count member. Let's drop the duplicate 'initialized' member to simplify the code a bit. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-4-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Move phy mode into struct qmp_phyStephen Boyd1-8/+7
The phy mode pertains to the phy itself, i.e. 'struct qmp_phy', not the wrapper, i.e. 'struct qcom_qmp'. Move the phy mode into the phy structure to more accurately reflect what is going on. This also cleans up 'struct qcom_qmp' so that it can eventually be the place where qmp wrapper wide data is located, paving the way for the USB3+DP combo phy. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-3-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy informationStephen Boyd1-11/+84
This binding only describes the USB phy inside the USB3 + DP "combo" phy. Add information for the DP phy and describe the sub-nodes that represent the DP and USB3 phys that exist inside the combo wrapper. Remove reg-names from required properties because it isn't required nor used by the kernel driver. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: <devicetree@vger.kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-2-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-23dt-bindings: phy: ti,phy-j721e-wiz: fix bindings for torrent phyTomi Valkeinen1-3/+10
When WIZ wraps a Cadence Torrent PHY (instead of Cadence Sierra PHY) there is a difference in the refclk-dig node: Torrent only has two clocks instead of Sierra's four clocks. Add minItems: 2 to solve this. Additionally, in our use case we only need to use assigned-clock for a single clock, but the current binding requires either no assigned-clocks or two. Fix this by adding minItems: 1 to all the assigned-clock properties. There was also an extra trailing whitespace, which this patch removes. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Link: https://lore.kernel.org/r/20200918083743.213874-2-tomi.valkeinen@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-23dt-bindings: phy: cdns,torrent-phy: add reset-namesTomi Valkeinen1-0/+10
Add reset-names as a required property. There are no dts files using torrent phy yet, so it is safe to add a new required property. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Link: https://lore.kernel.org/r/20200918083743.213874-1-tomi.valkeinen@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-22phy: rockchip-dphy-rx0: Include linux/delay.hTomasz Figa1-0/+1
Fix an implicit declaration of usleep_range(): drivers/phy/rockchip/phy-rockchip-dphy-rx0.c: In function 'rk_dphy_enable': drivers/phy/rockchip/phy-rockchip-dphy-rx0.c:203:2: error: implicit declaration of function 'usleep_range' [-Werror=implicit-function-declaration] Fixes: 32abcc4491c62 ("media: staging: phy-rockchip-dphy-rx0: add Rockchip MIPI Synopsys DPHY RX0 driver") Signed-off-by: Tomasz Figa <tfiga@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20200921225618.52529-1-tfiga@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-22phy: fix USB_LGM_PHY warning & build errorsRandy Dunlap1-0/+1
Fix a Kconfig warning that is causing lots of build errors when USB_SUPPORT is not set. USB_PHY depends on USB_SUPPORT but "select" doesn't care about dependencies, so this driver should also depend on USB_SUPPORT. It should not select USB_SUPPORT. WARNING: unmet direct dependencies detected for USB_PHY Depends on [n]: USB_SUPPORT [=n] Selected by [m]: - USB_LGM_PHY [=m] Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Li Yin <yin1.li@intel.com> Cc: Vadivel Murugan R <vadivel.muruganx.ramuthevar@linux.intel.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/d1dd0ddd-3143-5777-1c63-195e1a32f237@infradead.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add USB + SGMII/QSGMII multilink configurationSwapnil Jakhade1-0/+254
Add USB + SGMII/QSGMII multilink configuration sequences. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-14-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add PCIe + USB multilink configurationSwapnil Jakhade1-0/+216
Add PCIe + USB Unique SSC multilink configuration sequences. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-13-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add single link USB register sequencesSwapnil Jakhade1-1/+259
Add support for single link USB configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-12-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add single link SGMII/QSGMII register sequencesSwapnil Jakhade1-0/+89
Add support for single link SGMII/QSGMII configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-11-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_valsSwapnil Jakhade1-4/+18
Include PHY_PLL_CFG as a first register value to configure in link_cmn_vals array values. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-10-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add PHY link configuration sequences for single linkSwapnil Jakhade1-0/+44
Add support to configure link_cmn_vals and xcvr_diag_vals in case of single link PHY configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-9-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add clk changes for multilink configurationSwapnil Jakhade1-24/+17
Prepare and enable clock in probe instead of phy_init. Also, remove phy_exit callback. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-8-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Update PHY reset for multilink configurationSwapnil Jakhade1-7/+21
For multilink configuration, deassert PHY and link reset after PHY registers are configured in probe and only check link status in power_on callback. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-7-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add support for PHY multilink configurationSwapnil Jakhade1-26/+757
Added support for multilink configuration of Torrent PHY. Currently, maximum two links are supported. In case of multilink configuration, PHY needs to be configured for both the protocols simultaneously at the beginning as per the requirement of Torrent PHY. Also, register sequences for PCIe + SGMII/QSGMII Unique SSC PHY multilink configurations are added. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-6-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18dt-bindings: phy: Add PHY_TYPE_QSGMII definitionSwapnil Jakhade1-0/+1
Add definition for QSGMII phy type. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1600327846-9733-5-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add PHY APB reset supportSwapnil Jakhade1-0/+13
Add support for PHY APB reset and make it optional. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-4-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Check cmn_ready assertion during PHY power onSwapnil Jakhade1-1/+30
Check if cmn_ready is set after both PLL0 and PLL1 are locked. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add single link PCIe supportSwapnil Jakhade1-30/+266
Add single link PCIe register sequences in Torrent PHY driver. Also, add support for getting SSC type from DT. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18dt-bindings: phy: cadence-torrent: Update Torrent PHY bindings for generic useSwapnil Jakhade1-17/+60
Torrent PHY can be used in different multi-link multi-protocol configurations including protocols other than DisplayPort also, such as PCIe, USB, SGMII, QSGMII etc. Update the bindings to have support for these configurations. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-8-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18dt-bindings: phy: cadence-torrent: Add binding to specify SSC modeSwapnil Jakhade2-0/+22
Add binding to specify Spread Spectrum Clocking mode used. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1600280911-9214-7-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Check total lane count for all subnodes is within limitSwapnil Jakhade1-4/+15
Add checking if total number of lanes for all subnodes is not greater than number of lanes supported by PHY. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-6-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add separate regmap functions for torrent and DPSwapnil Jakhade1-33/+66
Added separate functions for regmap initialization of torrent PHY generic registers and DP specific registers. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-5-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Enable support for multiple subnodesSwapnil Jakhade1-15/+0
Enable support for multiple subnodes in torrent PHY to include multi-link combinations. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-4-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Use devm_platform_ioremap_resource() to get reg addressesSwapnil Jakhade1-6/+2
Use devm_platform_ioremap_resource() to get register addresses instead of boilerplate code. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Use of_device_get_match_data() to get driver dataSwapnil Jakhade1-8/+5
Use of_device_get_match_data() to get driver data instead of boilerplate code. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16phy: intel: Add Keem Bay eMMC PHY supportWan Ahmad Zainie3-0/+320
Add support for eMMC PHY on Intel Keem Bay SoC. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200913235522.4316-4-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16dt-bindings: phy: intel: Add Keem Bay eMMC PHY bindingsWan Ahmad Zainie1-1/+16
Binding description for Intel Keem Bay eMMC PHY. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200913235522.4316-3-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16phy: intel: Rename phy-intel to phy-intel-lgmWan Ahmad Zainie4-7/+7
Rename phy-intel-{combo,emmc}.c to phy-intel-lgm-{combo,emmc}.c to make drivers/phy/intel directory more generic for future use. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Link: https://lore.kernel.org/r/20200913235522.4316-2-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16phy: cadence: torrent: Constify regmap_config structsRikard Falkeborn1-6/+6
The regmap_config structs are never modified and can be made const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200912204639.501669-4-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16phy: cadence: salvo: Constify cdns_nxp_sequence_pairRikard Falkeborn1-3/+3
cdns_nxp_sequence_pair[] are never modified and can be made const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Reviewed-by: Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/20200912204639.501669-3-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16phy: cadence: Sierra: Constify static structsRikard Falkeborn1-12/+12
The static cdns_reg_pairs and regmap_config structs are not modified and can be made const. This allows the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200912204639.501669-2-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16phy: cadence-torrent: Set Torrent PHY attributesSwapnil Jakhade1-0/+4
Set Torrent PHY attributes bus_width, max_link_rate and mode for DisplayPort. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1599805114-22063-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16phy: Add new PHY attribute max_link_rateSwapnil Jakhade1-0/+2
Add new PHY attribute max_link_rate to struct phy_attrs. This indicates maximum link rate supported by PHY (in Mbps). Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1599805114-22063-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-11phy: Add USB3 PHY support for Intel LGM SoCRamuthevar Vadivel Murugan3-0/+295
Add support for USB PHY on Intel LGM SoC. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20200828022312.52724-3-vadivel.muruganx.ramuthevar@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>