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2019-12-05drm/amd/display: Change HDR_MULT checkKrunoslav Kovac1-5/+1
[Why] Currently we require HDR_MULT >= 1.0 There are scenarios where we need < 1.0 [How] Only guard against 0 - it will black-screen image. It is up to higher-level logic to decide what HDR_MULT values are allowed in each particular case. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: 3.2.62Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Implement DePQ for DCN2Reza Amini2-0/+8
[Why] Need support for more color management in 10bit surface. [How] Provide support for DePQ for 10bit surface Signed-off-by: Reza Amini <Reza.Amini@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: update dispclk and dppclk vco frequencyEric Yang1-1/+1
Value obtained from DV is not allowing 8k60 CTA mode with DSC to pass, after checking real value being used in hw, find out that correct value is 3600, which will allow that mode. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Fix screen tearing on vrr testsAmanda Liu2-20/+13
[Why] Screen tearing is present in tests when setting the frame rate to certain fps [How] Revert previous optimizations for low frame rates. Signed-off-by: Amanda Liu <amanda.liu@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: fix cursor positioning for multiplane casesAric Cyr1-9/+24
[Why] Cursor position needs to take into account plane scaling as well. [How] Translate cursor coords from stream space to plane space. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Limit NV12 chroma workaroundAnthony Koo1-1/+1
[Why] It is causing green Line at the bottom of SDR 480p MPO playback [How] Limit workaround to vertical > 512 Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: add dsc policy getterWenjing Liu2-42/+75
dc needs to expose its internal dsc policy. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: remove spam DSC logWenjing Liu1-1/+0
[why] add_dsc_to_stream_resource could be called for validation. Failing validation is completely fine. However failing it inside commit streams is bad. This code could be triggered for both contexts. The function itself cannot distinguish the caller, which makes it impossible to output the log only in the meaningful case (commit streams). Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: add dc dsc functions to return bpp range for pixel encodingWenjing Liu2-9/+37
[why] Need to support 6 bpp for 420 pixel encoding only. [how] Add a dc function to determine what bpp range can be supported for given pixel encoding. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Remove redundant callNoah Abradjian1-2/+0
[Why] I was advised that we don't need this call of program_front_end, as earlier and later calls in the same sequence are sufficient. [How] Remove first call of program_front_end in dc_commit_state_no_check. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Modify logic for when to wait for mpcc idleNoah Abradjian1-9/+9
[Why] I was advised that we may need to check for mpcc idle in more cases than just when opp_changed is true. Also, mpcc_inst is equal to pipe_idx, so remove for loop. [How] Remove opp_changed flag check and mpcc_inst loop. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: check for repeater when setting aux_rd_interval.abdoulaye berthe1-2/+2
[Why] When training with repeater the aux read interval must be set to repeater specific aux_red_interval. This value is always 100us for CR. [How] Check for repeater when setting the aux_rd_interval in channel equalization. Use the right offset in the aux_rd_interval array Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: George Shen <George.Shen@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Remove flag check in mpcc updateNoah Abradjian1-6/+0
[Why] MPCC programming was being missed during certain split pipe enables due to full_update flag not being true. This caused a momentary flash on half the screen. After discussion, determined we should not have that flag check within update_mpcc, as it should always perform full programming when called. [How] Remove flag check. We call update_blending within insert_plane, so we do not need to replace its call from the if block. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: update sr latency for renoir when using lpddr4Joseph Gravenor1-8/+8
[Why] DF team has produced more optimized sr latency numbers, for lpddr4 [How] change the sr laency in the lpddr4 wm table to the new latency number Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Add shared DMCUB/driver firmware state cache windowNicholas Kazlauskas7-11/+125
[Why] Scratch registers are limited on the DMCUB and we have an expanding list of state to track between driver and DMCUB. [How] Place shared state in cache window 6. The cache window size is aligned to the size of the cache line on the DMCUB to make it easy to invalidate. The shared state is intended to be read only from driver side so it's been marked as const. The use of volatile is intentional. The memory for the shared firmware state is memory mapped from the framebuffer memory. The DMCUB will flush its cache after modifying the region. There's no way for x86 to known whether this data is stale or not so we want to intentionally disable optimization to force the read at every access. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Split DMUB cmd type into type/subtypeNicholas Kazlauskas5-34/+112
[Why] Commands will be considered a stable ABI between driver and firmware. Commands are also split between DC commands, DAL feature commands, and VBIOS commands. Commands are currently not designated to a specific ID and the enum does not provide a stable ABI. We currently group all of these into a single command type of 8-bits. With the stable ABI consideration in mind it's not unreasonable to run out of command IDs. For cleaner separation and versioning split the commands into a main type and a subtype. [How] For commands where performance matters (like reg sequences) these are still considered main commands. Sub commands will be split by ownership/feature. Update existing command sequences to reflect new changes. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Return a correct error valueMikita Lipski1-3/+3
[why] The function is expected to return instance of the timing generator therefore we shouldn't be returning boolean in integer function, and we shouldn't be returning zero so changing it to -1. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Save/restore link setting for disable phy when link retrainingHugo Hu1-2/+3
[Why] The link setting will be modify after disable phy and due to DP Compliance Fails. [How] Save and resotre link setting for disable link phy when link retraining. Signed-off-by: Hugo Hu <hugo.hu@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: add DP protocol versionAnthony Koo2-0/+7
[Why] We want to know DP protocol version [How] In DC create we initialize a cap to indicate the max DP protocol version supported Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: update p-state latency for renoir when using lpddr4Joseph Gravenor1-4/+4
[Why] DF team has produced more optimized latency numbers, for lpddr4 [How] change the p-state laency in the lpddr4 wm table to the new latency number Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Implement DePQ for DCN1Reza Amini3-9/+38
[Why] Need support for more color management in 10bit surface. [How] Provide support for DePQ for 10bit surface Signed-off-by: Reza Amini <Reza.Amini@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Reset steer fifo before unblanking the streamNikola Cornij1-2/+10
[why] During mode transition steer fifo could overflow. Quite often it recovers by itself, but sometimes it doesn't. [how] Add steer fifo reset before unblanking the stream. Also add a short delay when resetting dig resync fifo to make sure register writes don't end up back-to-back, in which case the HW might miss the reset request. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: fix dml20 min_dst_y_next_start calculationDmytro Laktyushkin1-2/+1
Bring this calculation in line with HW programming guide. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Disable chroma viewport w/a when rotated 180 degreesMichael Strauss6-7/+17
[WHY] Previous Renoir chroma viewport workaround fixed an MPO flicker by increasing the chroma viewport size. However, when the MPO plane is rotated 180 degrees, the viewport is read in reverse. Since the workaround increases viewport size, when reading in reverse it causes a vertical chroma offset. [HOW] Pass rotation value to viewport set functions Temporarily disable the chroma viewport w/a when hubp is rotated 180 degrees Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: add log for lttprabdoulaye berthe1-32/+93
Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: fixed that I2C over AUX didn't read data issueBrandon Syu2-2/+2
[Why] The variable mismatch assignment error. [How] To use uint32_t replace it. Signed-off-by: Brandon Syu <Brandon.Syu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Change the delay time before enabling FECLeo (Hanghong) Ma1-1/+8
[why] DP spec requires 1000 symbols delay between the end of link training and enabling FEC in the stream. Currently we are using 1 miliseconds delay which is not accurate. [how] One lane RBR should have the maximum time for transmitting 1000 LL codes which is 6.173 us. So using 7 microseconds delay instead of 1 miliseconds. Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: 3.2.61Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: fix dprefclk and ss percentage reading on RNEric Yang3-13/+5
[Why] Before was using HW counter value to determine the dprefclk. Which take into account ss, but has large variation, not good enough for generating audio dto. Also, the bios parser code to get the ss percentage was not working. [How] After this change, dprefclk is hard coded, same as on RV. We don't expect this to change on Renoir. Modified bios parser code to get the right ss percentage. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: have two different sr and pstate latency tables for renoirJoseph Gravenor1-34/+80
[Why] new sr and pstate latencies are optimized for the case when we are not using lpddr4 memory [How] have two different wm tables, one for the lpddr case and one for non lpddr case Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Fixed kernel panic when booting with DP-to-HDMI dongleDavid Galiffi1-1/+1
[Why] In dc_link_is_dp_sink_present, if dal_ddc_open fails, then dal_gpio_destroy_ddc is called, destroying pin_data and pin_clock. They are created only on dc_construct, and next aux access will cause a panic. [How] Instead of calling dal_gpio_destroy_ddc, call dal_ddc_close. Signed-off-by: David Galiffi <David.Galiffi@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: populate bios integrated info for renoirJoseph Gravenor2-4/+7
[Why] When video_memory_type bw_params->vram_type is assigned, wedistinguish between Ddr4MemType and LpDdr4MemType. Because of this we will never report that we are using LpDdr4MemType and never re-purpose WM set D [How] populate bios integrated info for renoir by adding the revision number for renoir and use that integrated info table instead of of asic_id to get the vram type Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Program CW5 for tracebuffer for dcn20Nicholas Kazlauskas1-0/+7
[Why] On dcn21 this is programmed for tracebuffer support but isn't being programmed on dcn20. DMCUB execution hits an undefined address 65000000 on tracebuffer access. [How] Program CW5. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Return DMUB_STATUS_OK when autoload unsupportedNicholas Kazlauskas1-2/+8
[Why] Not having support for autoload isn't an error. If the DMUB firmware doesn't support it then don't return DMUB_STATUS_INVALID. [How] Return DMUB_STATUS_OK when ->is_auto_load_done is NULL. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Only wait for DMUB phy init on dcn21Nicholas Kazlauskas5-8/+8
[Why] The wait for PHY init won't finish if the firmware doesn't support it. [How] Only hook this functionality up on DCN21 and move it out of DCN20. For ASIC without support then this should return OK so we don't hang while waiting in DC. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Add DMCUB__PG_DONE trace code enumYongqiang Sun1-0/+1
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Disable link before reenableLucy Li1-47/+52
[Why] Black screen seen after display is disabled then re-enabled. Caused by difference in link settings when switching between different resolutions. [How] In PnP case, or whenever the display is still enabled but the driver is unloaded, disable link before re-enabling with new link settings. Signed-off-by: Lucy Li <lucy.li@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Reset PHY in link re-trainingPaul Hsieh4-53/+66
[Why] Link training failed randomly when plugging USB-C display in/out. [How] If link training failed, reset PHY in link re-training. Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Wrong ifdef guards were used around DML validationJaehyun Chung3-1/+3
[Why] Wrong guards were causing the debug option not to run. [How] Changed the guard to the correct one, matching the rq, ttu, dlg regs struct members that need to be guarded. Also log a message when validation starts. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: fix DalDramClockChangeLatencyNs overrideJoseph Gravenor1-1/+4
[why] pstate_latency_us never gets updated from the hard coded value in rn_clk_mgr.c [how] update the wm table's values before we do calculations with them Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Map DSC resources 1-to-1 if numbers of OPPs and DSCs are equalNikola Cornij1-3/+10
[why] On ASICs where number of DSCs is the same as OPPs there's no need for DSC resource management. Mappping 1-to-1 fixes mode-set- or S3- -related issues for such platforms. [how] Map DSC resources 1-to-1 to pipes only if number of OPPs is the same as number of DSCs. This will still keep other ASICs working. A follow-up patch to fix mode-set issues on those ASICs will be required if testing shows issues with mode set. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: Fix Dali clk mgr constructMichael Strauss2-7/+12
[WHY] Dali is currently being misinterpreted as Renoir, as a result uses wrong clk mgr constructor [HOW] Add check to init Dali as Raven2 before it can be misidentified Clean up & fix Raven2 & Dali ASIC checks Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: add separate of private hwss functionsAnthony Koo27-470/+525
[Why] Some function pointers in the hwss function pointer table are meant to be hw sequencer entry points to be called from dc. However some of those function pointers are not meant to be entry points, but instead used as a code reuse/inheritance tool called directly by other hwss functions, not by dc. Therefore, we want a more clear separation of which functions we determine to be interface functions vs the functions we use within hwss. [How] DC interface functions will be stored in: struct hw_sequencer_funcs Functions used within HWSS will be stored in: struct hwseq_private_funcs Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: rename core_dc to dcAnthony Koo12-107/+102
[Why] First, to make code more consistent Second, to get rid of those scenario where we create a second local pointer to dc when it's already passed in. [How] Rename core_dc to dc Remove duplicate local pointers to dc Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amd/display: update sr and pstate latencies for RenoirEric Yang3-7/+26
[Why] DF team has produced more optimized latency numbers. [How] Add sr latencies to the wm table, use different latencies for different wm sets. Also fix bb override from registery key for these latencies. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amdgpu: reduce redundant uvd context lost warning messageLe Ma1-4/+7
Move the print out of uvd instance loop in amdgpu_uvd_suspend v2: drop unnecessary brackets v3: grab ras_intr state once for multiple times use Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amdgpu: clear err_event_athub flag after reset exitLe Ma2-0/+8
Otherwise next err_event_athub error cannot call gpu reset. And following resume sequence will not be affected by this flag. v2: create function to clear amdgpu_ras_in_intr for modularity of ras driver Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amdgpu: support full gpu reset workflow when ras err_event_athub occursLe Ma1-6/+11
This athub fatal error can be recovered by baco without system-level reboot, so add a mode to use baco for the recovery. Not affect the default psp reset situations for now. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-05drm/amdgpu: add concurrent baco reset support for XGMILe Ma2-12/+72
Currently each XGMI node reset wq does not run in parrallel if bound to same cpu. Make change to bound the xgmi_reset_work item to different cpus. XGMI requires all nodes enter into baco within very close proximity before any node exit baco. So schedule the xgmi_reset_work wq twice for enter/exit baco respectively. To use baco for XGMI, PMFW supported for baco on XGMI needs to be involved. The case that PSP reset and baco reset coexist within an XGMI hive never exist and is not in the consideration. v2: define use_baco flag to simplify the code for xgmi baco sequence Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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