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2018-10-05dt-bindings: mediatek: Add JPEG Decoder binding for MT7623Matthias Brugger1-0/+1
This patch adds a binding documentation for the JPEG Decoder of the MT7623 SoC. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-10-05dt-bindings: iommu: mediatek: Add binding for MT7623Matthias Brugger1-1/+3
This patch adds binding documentation for MT7623 SoC. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-10-05dt-bindings: clock: mediatek: add support for MT7623Matthias Brugger11-0/+11
This patch adds bindings for apmixedsys, audsys, bpsys, ethsys, hifsys, imgsys, infracfg, mmsys, pericfg, topckgen and vdecsys for MT6723. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-10-04ARM: dts: mvebu: armada-385-db-88f6820-amc: auto-detect nand ECC properitesChris Packham1-2/+0
This board has a Micron MT29F8G08ABACAWP chip which requires a ECC strength of 8/512. Rather than hard coding any particular strength the the nand controller auto-detect the ECC strength based on the ONFI data. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-10-04ARM: dts: da850-lego-ev3: slow down A/DC as much as possibleDavid Lechner1-1/+2
Due to the electrical design of the A/DC circuits on LEGO MINDSTORMS EV3, if we are reading analog values as fast as possible (i.e. using DMA to service the SPI) the A/DC chip will read incorrect values - as much as 0.1V off when the SPI is running at 10MHz. (This has to do with the capacitor charge time when channels are muxed in the A/DC.) This patch slows down the SPI as much as possible (if CPU is at 456MHz, SPI runs at 1/2 of that, so 228MHz and has a max prescalar of 256, so we could get ~891kHz, but we're just rounding it to 1MHz). We also use the max allowable value for WDELAY to slow things down even more. These changes reduce the error of the analog values to about 5mV, which is tolerable. Commits a3762b13a596 ("spi: spi-davinci: Add support for SPI_CS_WORD") and e2540da86ef8 ("iio: adc: ti-ads7950: use SPI_CS_WORD to reduce CPU usage") introduce changes that allow DMA transfers to be used, so this slow down is needed now. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2018-10-04ARM: dts: da850-evm: Enable tca6416 on baseboardAdam Ford1-0/+6
There is a GPIO expander on both the UI board as well as the baseboard. This patch enables the second tca6416 and identifies it as being on the baseboard using _bb as the suffix. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2018-10-04arm64: dts: uniphier: Add USB2 PHY nodesKunihiko Hayashi1-0/+27
Add nodes of USB2 physical layer for UniPhier SoC. This supports LD11. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-04arm64: dts: uniphier: Add USB3 controller nodesKunihiko Hayashi5-0/+450
Add USB3 controller nodes including usb-core, resets, regulator, ss-phy and hs-phy. This supports for LD20, PXs3 and the boards. This includes additional efuse nodes for obtaining PHY trimming values. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-04ARM: dts: uniphier: Add USB2 PHY nodesKunihiko Hayashi1-1/+34
Add nodes of USB2 physical layer for UniPhier SoC. This supports Pro4. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-04ARM: dts: uniphier: Add USB3 controller nodesKunihiko Hayashi8-0/+318
Add USB3 controller nodes including usb-core, resets, regulator, ss-phy and hs-phy. This supports for Pro4, PXs2 and the boards. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-03arm64: dts: meson-axg: s400: disable emmcJerome Brunet1-1/+1
While it is possible to rework the s400 board to solder an eMMC on it, it is not the default option and most boards are fitted with a NAND instead. Let's disable the emmc device by default to reflect this. The board equipped with an eMMC will just have to alter the DT in the bootloader, like we do for the reserved memory regions. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-10-03arm64: dts: meson-axg: s400: add missing emmc pwrseqJerome Brunet1-0/+2
eMMC pwrseq is defined in the s400 dts but not used in the emmc node. This is probably just a copy/paste error Fixes: 221cf34bac54 ("ARM64: dts: meson-axg: enable the eMMC controller") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-10-03arm64: dts: clearfog-gt-8k: add PCIe slot descriptionBaruch Siach1-0/+7
This adds support for the PCIe interface on the CON4 mini-PCIe connector. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-10-03ARM: dts: at91: sama5d4_xplained: even nand memory partitionsTudor Ambarus1-3/+8
sama5d4_xplained, ssam9x5cm, sama5d2_ptc_ek and sama5d3_xplained nand flashes have a common memory map. Even the nand memory partitions to match our NAND flash map available at: http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.png Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2018-10-03ARM: dts: at91: sama5d3_xplained: even nand memory partitionsTudor Ambarus1-3/+8
sama5d3_xplained, sam9x5cm, sama5d2_ptc_ek and sama5d4_xplained nand flashes have a common memory map. Even the nand memory partitions to match our nand flash map available at: http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.png Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2018-10-03ARM: dts: at91: at91sam9x5cm: even nand memory partitionsTudor Ambarus1-3/+13
sam9x5cm, sama5d2_ptc_ek, sama5d3_xplained and sama5d4_xplained nand flashes have a common memory map. Even the nand memory partitions to match our nand flash map available at: http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.png Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2018-10-03ARM: dts: at91: sama5d2_ptc_ek: fix bootloader env offsetsTudor Ambarus1-4/+4
The offsets for the bootloader environment and its redundant partition were inverted. Fix the addresses to match our nand flash map available at: http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.png Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2018-10-03ARM: dts: at91: at91sam9x5cm: fix addressable nand flash sizeTudor Ambarus1-1/+1
at91sam9x5cm comes with a 2Gb NAND flash. Fix the rootfs size to match this limit. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2018-10-03ARM: dts: at91: sama5d4_xplained: fix addressable nand flash sizeTudor Ambarus1-1/+1
sama5d4_xplained comes with a 4Gb NAND flash. Increase the rootfs size to match this limit. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2018-10-03arm64: dts: marvell: add CP110 ICU SEI subnodeMiquel Raynal1-0/+8
The ICU handles several interrupt groups, each of them being a subpart of the ICU node. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-10-03arm64: dts: marvell: use new bindings for CP110 interruptsMiquel Raynal1-67/+74
Create an ICU subnode for the NSR interrupts. This subnode becomes the CP110 interrupt parent, removing the need for the ICU_GRP_NSR parameter. Move all DT110 nodes to use these new bindings. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-10-03arm64: dts: uniphier: add SD controller nodesMasahiro Yamada3-0/+36
Add SD controller nodes for LD20 and PXs3. LD20 does not support the UHS mode, while PXs3 supports it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-03ARM: dts: uniphier: add SD/eMMC controller nodesMasahiro Yamada14-0/+221
Add SD controller nodes for LD4, Pro4, sLD8, Pro5, and PXs2. This is also used as an eMMC controller for LD4, Pro4, and sLD8. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-02arm64: dts: marvell: add AP806 SEI subnodeMiquel Raynal1-0/+9
Add the System Error Interrupt node, representing an IRQ chip which is part of the GIC. The SEI node aggregates interrupts from the AP through wired interrupts, and from the CPs through MSIs. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-10-02arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8Korenbh2-0/+31
This patch adds CPU deep Idle and Cluster deep Idle states BUT it defines the idle state for each cpu (defined under cpu-idle-states parameter) only for the quad version therefore it does NOT activate CPU Idle capability for the other version. [gregory: extract from a larger patch] Signed-off-by: orenbh <orenbh@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-10-02arm64: dts: marvell: Add node labels for the cpusGregory CLEMENT5-16/+16
Aligned with what we have done for the others nodes. It will also allow to easily modify the cpu configuration at board (or sub-SoC) level. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-30ARM: dts: qcom: Update coresight bindings for hardware portsSuzuki K Poulose2-79/+96
Switch to the new hardware port bindings for coresight Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-30Revert "dt-bindings: thermal: qcom-spmi-temp-alarm: Fix documentation of 'reg'"Andy Gross1-2/+3
This reverts commit e704472616d7e185b839991b611a77711dbb22e3. Already picked up via Eduardo's thermal tree Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-30Revert "dt-bindings: iio: vadc: Fix documentation of 'reg'"Andy Gross1-2/+2
This reverts commit 7028cae1857cc2c6acc69586584e92d044027154. Already picked up via iio tree. Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-30arm64: dts: actions: s700: Set UART clock references from CMUSaravanan Sekar2-7/+7
Remove fixed clock in Cubieboard 7 and use Clock Management Unit clocks for all UART nodes in Actions Semi S700 SoC. Signed-off-by: Parthiban Nallathambi <pn@denx.de> Signed-off-by: Saravanan Sekar <sravanhome@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [AF: Moved/added to SoC] Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s700: Add Clock Management UnitSaravanan Sekar1-0/+14
Add Clock Management Unit for Actions Semi S700 SoC. Signed-off-by: Parthiban Nallathambi <pn@denx.de> Signed-off-by: Saravanan Sekar <sravanhome@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Add DMA ControllerManivannan Sadhasivam1-0/+13
Add DMA controller node for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900-bubblegum-96: Enable I2C1 and I2C2Manivannan Sadhasivam1-0/+43
Add pinctrl definitions for Actions Semiconductor S900 I2C controllers. Pinctrl definitions are only available for I2C0, I2C1, and I2C2. Enable I2C1 and I2C2 exposed on the low speed expansion connector in Bubblegum-96 board. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [AF: Squashed] Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Add I2C controller nodesManivannan Sadhasivam1-0/+60
Add I2C controller nodes for Actions Semiconductor S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [AF: Squashed/added clocks, dropped pinctrl properties for now] Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900-bubblegum-96: Add gpio line namesManivannan Sadhasivam1-0/+175
Add gpio line names to Actions Semi S900 based Bubblegum-96 board. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Add gpio properties to pinctrl nodeManivannan Sadhasivam1-0/+3
Add gpio properties to pinctrl node for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Add pinctrl nodeManivannan Sadhasivam1-0/+6
Add pinctrl nodes for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Add SPS nodeManivannan Sadhasivam1-0/+6
Add Actions Semi S900 Smart Power System (SPS) node. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Source CMU clock for UARTsManivannan Sadhasivam2-7/+7
Remove fixed clock in Bubblegum-96 board and source CMU (Clock Management Unit) clock for UART nodes in Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [AF: Move/add clocks to SoC] Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Add Clock Management Unit nodesManivannan Sadhasivam1-0/+20
Add Actions Semi S900 Clock Management Unit (CMU) nodes. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30dt-bindings: power: Add Actions Semi S900 SPSManivannan Sadhasivam2-0/+25
Define power domains for Actions Semi S900 SoC Smart Power System (SPS). Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30ARM: dts: imx: add i.mx6ulz and i.mx6ulz 14x14 evk supportAnson Huang3-1/+60
i.MX6ULZ is new SoC of i.MX6 family, compared to i.MX6ULL, it removes below modules: - UART5/UART6/UART7/UART8; - PWM5/PWM6/PWM7/PWM8; - eCSPI3/eCSPI4; - CAN1/CAN2; - FEC1/FEC2; - I2C3/I2C4; - EPIT2; - LCDIF; - GPT2; - ADC1; - TSC; This patch adds support for i.MX6ULZ and i.MX6ULZ 14x14 EVK board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-30dt-bindings: arm: add compatible for i.MX6ULZ 14x14 EVK boardAnson Huang1-0/+4
This patch adds compatible for i.MX6ULZ 14x14 EVK board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-30ARM: dts: imx53-ppd: Remove 'num-chipselects' propertyFabio Estevam1-1/+0
The 'num-chipselects' property is not a valid property according to Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt, so let's remove it. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-30ARM: dts: vf610-twr: Switch to SPDX identifierFabio Estevam1-40/+3
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-30ARM: dts: vf: Switch to SPDX identifierFabio Estevam3-120/+10
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-29ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device treesChen-Yu Tsai5-0/+57
Bananapi released an updated revision of the H3/H5 based Bananapi M2+. Version 1.2 enables voltage control for the CPU's regulator by using a GPIO line to toggle a MOSFET that can change the effective resistance value in the regulator's feedback network. This patch adds a common .dtsi file for this new revision, which includes the original common sunxi-bananapi-m2-plus.dtsi file, and adds the GPIO-controlled regulator and a cpu-supply reference. H3 and H5 variant dts files are added as well. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-09-29ARM: dts: sun8i-h3: Add Video Engine and reserved memory nodesPaul Kocialkowski1-0/+25
This adds nodes for the Video Engine and the associated reserved memory for the H3. Up to 96 MiB of memory are dedicated to the CMA pool. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-09-29arm64: dts: allwinner: h5: Add device tree for Bananapi M2 Plus H5Chen-Yu Tsai2-0/+12
The Bananapi M2 Plus H5 is a variant of the original Bananapi M2 Plus, with the H3 SoC replaced with an H5. Everything else is the same. Add a stub device tree incorporating the shared bananapi-m2-plus dtsi file. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-09-29ARM: dts: sun8i: h3: Split out non-SoC-specific parts of Bananapi M2 PlusChen-Yu Tsai2-188/+233
Three more variants of the Bananapi M2 Plus have been introduced. One with the H5 instead of the H3, another with the H2+ instead, and the last with the H3 but with WiFi and eMMC removed. All these variants use the same board. This patch splits out the non-SoC-specific parts of the device tree, so that they can be shared among all the variants. The original Bananapi M2 Plus has been renamed to Bananapi M2 Plus H3. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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