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2016-06-24arm64: dts: msm8996: add sdc2 supportSrinivas Kandagatla1-0/+15
This patch adds support to sdc2 sdhci controller, which is used on some of the boards. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add sdc2 pinctrlSrinivas Kandagatla1-0/+48
This patch adds pinctrl required for sdhci for external sd card controller. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add support to blsp2_spi5Srinivas Kandagatla1-0/+15
This patch adds support to blsp2_spi5 device, which is used in some of the APQ8096 based boards. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add support to blsp2_spi5 pinctrlSrinivas Kandagatla1-0/+34
This patch adds pinctrl required for blsp2_spi5 device. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add support to blsp1_spi0Srinivas Kandagatla1-0/+15
This patch adds support to blsp1_spi0 which is used on some of APQ8096 based boards. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add support to blsp1_spi0 pinctrlSrinivas Kandagatla1-0/+34
This patch adds pinctrl nodes required for blsp1_spi0. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add support to blsp2_i2c0Srinivas Kandagatla1-0/+15
This patch adds support to blsp2_i2c0, which is used on some of the APQ8096 based boards. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add support to blsp2_i2c0 pinctrlSrinivas Kandagatla1-0/+24
This patch adds support to blsp2_i2c0 pinctrl. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add support to blsp2_i2c1Srinivas Kandagatla1-0/+15
This patch adds support to blsp2_i2c1, which is used in one of the apq8096 based boards. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add blsp2_i2c1 pinctrlSrinivas Kandagatla1-0/+24
This patch adds support to blsp2_i2c1 pinctrl nodes. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add support to blsp1_i2c2 deviceSrinivas Kandagatla1-0/+15
This patch adds blsp1_i2c2 support, as this bus is used on some of the apq8096 boards. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add blsp1_i2c2 pinctrl nodes.Srinivas Kandagatla1-0/+24
This patch adds pinctrl nodes required for blsp1_i2c2. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add support blsp2_uart2Srinivas Kandagatla1-0/+10
This patch adds bslp2_uart2 node in soc so that boards that use this uart can enable it. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add blsp2_uart2 pinctrl nodes.Srinivas Kandagatla1-0/+50
This patch adds blsp2_uart2 pinctrl nodes. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add blsp2_uart1 pinctrlSrinivas Kandagatla2-0/+66
This patch adds 2pin and 4 pin uart pinctrl support for blsp2_uart1 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24arm64: dts: msm8996: add msmgpio labelSrinivas Kandagatla1-1/+1
This patch adds msmgpio label for pin and gpio controller so that it can referenced in dedicated pins file and other board level gpios. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-21arm64: dts: ls2080a: Add cache nodes for cacheinfo supportLi Yang1-0/+24
Adds the cache nodes and next-level-cache property for the cacheinfo to work. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-21arm64: dts: ls1043a: Add cache nodes for cacheinfo supportLi Yang1-0/+8
Adds the cache nodes and next-level-cache property for the cacheinfo to work. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-20arm64: dts: apm: Remove unused qmlclk node on X-Gene 1Duc Dang1-10/+0
Node qmlclk has no consumer, so remove it. Signed-off-by: Duc Dang <dhdang@apm.com>
2016-06-20arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoCDuc Dang1-4/+4
Correct X-Gene 2 timer interrupt polarity as low-level triggered. Signed-off-by: Duc Dang <dhdang@apm.com>
2016-06-20arm64: dts: apm: Remove leading '0x' from unit addressesBjorn Helgaas1-16/+16
Unit addresses should not have a leading '0x'. Remove them. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Duc Dang <dhdang@apm.com>
2016-06-20arm64: dts: apm: Use lowercase consistently for hex constantsBjorn Helgaas3-40/+40
The convention in these files is to use lowercase for "0x" prefixes and for the hex constants themselves, but a few changes didn't follow that convention, which makes the file annoying to read. Use lowercase consistently for the hex constants. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Duc Dang <dhdang@apm.com>
2016-06-16arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodesLiu Gang1-0/+3
The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-16bindings: PCI: layerscape: Add 'dma-coherent' propertyLiu Gang1-0/+4
Add 'dma-coherent' description for PCI nodes. The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-14arm64: dts: uniphier: add /memreserve/ for spin-table release addressMasahiro Yamada1-0/+2
As Documentation/arm64/booting.txt says, the cpu-release-addr location should be reserved. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-14arm64: dts: uniphier: change cpu-release-addressMasahiro Yamada1-4/+4
At first, 256 byte of the head of DRAM space was reserved for some reasons. However, as the progress of development, it turned out unnecessary, and it was never used in the end. Move the CPU release address to leave no space. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-14arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCsMasahiro Yamada1-3/+7
This node consists of various system-level configuration registers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-12ARM: dts: msm8916: Update reserved-memoryBjorn Andersson1-3/+38
Update reserved-memory in accordance with memory the detailed memory map for 8916, so that we will be able to reference the firmware memory regions. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-12arm64: dts: msm8916: Add SCM firmware nodeAndy Gross1-0/+8
This adds the devicetree node for the SCM firmware. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-12arm64: dts: qcom: Add msm8916 PMU nodeStephen Boyd1-0/+5
Add the PMU so we can get proper perf event support on this SoC. Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-12ARM64: dts: Add PSCI cpuidle support for MSM8916Lina Iyer1-0/+24
Add device bindings for CPUs to suspend using PSCI as the enable-method. Cc: <devicetree@vger.kernel.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Tested-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-12arm64: dts: qcom: apq8016-sbc: enable bam dma node.Srinivas Kandagatla1-0/+4
This patch enables bam dma node, dma is used for both tx and rx on spi and on high speed serial. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-12arm64: dts: apq8016-sbc: Add DT node for the uSD SDHC interfaceGeorgi Djakov1-0/+12
Add the necessary properties to enable the SD-card on db410c boards. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-11arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 nodeRajesh Bhagat1-0/+3
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-11arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 nodeRajesh Bhagat1-0/+2
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-09arm64: dts: fsl: Update address-cells and reg properties of cpu nodesAlison Wang2-14/+14
MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1, since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update the #address-cells and reg properties accordingly. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-03arm64: dts: Add dts files for LG Electronics's lg1313 SoCChanho Min3-0/+388
Add dtsi file to support lg1313 SoC which based on Cortex-A53. Also add dts file to support lg1312 reference board which based on lg1313 SoC. Signed-off-by: Chanho Min <chanho.min@lge.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-01ARM64: dts: amlogic: Enable Reset Controller on GXBB-based platformsNeil Armstrong1-0/+7
Update DTSI file to add the reset controller node. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-01ARM64: dts: amlogic: gxbb: add ethernetKevin Hilman3-0/+45
Add node for ethernet interface and pinctrl pins. Enable on odroid-C2 and P20x boards. Acked-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-01ARM64: dts: amlogic: gxbb: pinctrl: add/update UARTKevin Hilman2-1/+42
Add DT nodes for additional UARTs (UART B & C in EE domain) and add pins for all EE domain UARTs. Acked-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-01ARM64: dts: amlogic: add pins for EMMC, SDKevin Hilman1-0/+21
Acked-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-01ARM64: dts: amlogic: Enable pin controller on GXBB-based platformsCarlo Caione4-0/+59
Update DTS and DTSI files to enable the pin controller. We also now support the blinking blue LED on the Odroid-C2. Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-01documentation: Add compatibles for Amlogic Meson GXBB pin controllersCarlo Caione1-0/+2
Add the two new compatibles for the Amlogic Meson GXBB pin controllers. Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-06-01ARM64: dts: amlogic: Add hiu and periphs busesCarlo Caione1-0/+16
Add two new buses in the DTS: hiu and periphs buses. In the Amlogic S905/GXBB SoC several devices (clock / eth / pin controllers, etc...) are mapped under these two buses. Add them in the DT before starting to add new devices. Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-05-31arm64: dts: NS2: Add CCI-400 PMU supportJon Mason1-0/+20
Add support to the Northstar 2 Device tree file for the ARM CCI-400 PMU. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-05-31arm64: dts: NS2: Add all of the UARTsJon Mason2-0/+46
Add all of the UARTs present on NS2 and enable them in the SVK device tree file. Also, do some magic to make sure that uart3 is discovered as ttyS0 (as that is the console UART). Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-05-31arm64: dts: Enable GPIO for Broadcom NS2 SoCYendapally Reddy Dhananjaya Reddy1-0/+19
This enables the GPIO support for Broadcom NS2 SoC Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-05-31arm64: dts: enable pinctrl for Broadcom NS2 SoCYendapally Reddy Dhananjaya Reddy2-0/+16
This enables the pinctrl support for Broadcom NS2 SoC Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-05-31arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2Anup Patel2-0/+55
We have one dual-port SATA3 AHCI controller present in NS2 SoC. This patch enables SATA3 AHCI controller and SATA3 PHY for NS2 SoC in NS2 DT. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-05-31dt-bindings: ata: add compatible string for iProc AHCI controllerAnup Patel1-0/+1
The Broadcom iProc SoCs have AHCI compliant SATA controller. This patch adds common compatible string for AHCI SATA controller on iProc SoCs. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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