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2020-07-15arm64: tegra: Enable Tegra VI CSI support for Jetson NanoSowjanya Komatineni1-0/+10
This patch enables VI and CSI in device tree for Jetson Nano. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: jetson-tx1: Add camera suppliesSowjanya Komatineni1-0/+38
Jetson TX1 development board has a camera expansion connector which has 2V8, 1V8 and 1V2 supplies to power up the camera sensor on the supported camera modules. Camera module designed as per Jetson TX1 camera expansion connector may use these supplies for camera sensor avdd 2V8, digital core 1V8, and digital interface 1V2 voltages. These supplies are from fixed regulators on TX1 carrier board with enable control signals from I2C GPIO expanders. This patch adds these camera supplies to Jetson TX1 device tree to allow using these when a camera module is used. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix order of XUSB controller clocksThierry Reding1-2/+2
This is purely to make the json-schema validation tools happy because they cannot deal with string arrays that may be in arbitrary order. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Rename cbb@0 to bus@0 on Tegra194Thierry Reding3-17/+17
The control backbone is a simple-bus and hence its device tree node should be named "bus@<unit-address>" according to the bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Sort nodes by unit-address on Jetson NanoThierry Reding1-8/+8
Move the usb@700d0000 node to the correct place in the device tree, ordered by unit-address. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Various fixes for PMICsThierry Reding2-26/+25
Standardize on "pmic" as the node name for the PMIC on Tegra210 systems and use consistent names for pinmux and GPIO hog nodes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Rename agic -> interrupt-controllerThierry Reding3-3/+3
Device tree nodes for interrupt controllers should be named "interrupt- controller", so rename the AGIC accordingly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix indentation in Tegra194 device treeThierry Reding1-1/+1
Properly indent subsequent lines so that they align with the first line. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix indentation in Tegra132 device treeThierry Reding1-1/+1
Properly indent subsequent lines so that they align with the first line. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Remove unused interrupts from Tegra194 AON GPIOThierry Reding1-4/+1
The AON GPIO controller on Tegra194 currently only uses a single interrupt, so remove the extra ones. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Use standard names for SRAM nodesThierry Reding2-10/+6
SRAM nodes should be named sram@<unit-address> to match the bindings. While at it, also remove the unneeded, custom compatible string for SRAM partition nodes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Do not mark display hub as simple busThierry Reding2-2/+2
The display hub on Tegra186 and Tegra194 is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix {clock,reset}-names orderingThierry Reding1-6/+6
It's very difficult to describe string lists that can be in arbitrary order using the json-schema based validation tooling. Since the OS is not going to care either way, take the easy way out and reorder these entries to match the order defined in the bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Remove XUSB pad controller interrupt from XUSB nodeThierry Reding2-4/+2
The XUSB controller doesn't need the XUSB pad controller's interrupt, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Use standard EEPROM propertiesThierry Reding5-12/+12
The address-bits and page-size properties that are currently used are not valid properties according to the bindings. Use the address-width and pagesize properties instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Update USB connector nodesThierry Reding3-19/+18
Use the preferred {id,vbus}-gpios over the {id,vbus}-gpio properties and fix the ordering of compatible strings (most-specific ones should come first). Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Remove unneeded power suppliesThierry Reding1-4/+0
On Tegra186 and later, the BPMP is responsible for enabling/disabling the PCIe related power supplies of the pad controller and there is no need for the operating system to control them, so they can be removed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Add missing #phy-cells property to USB PHYsThierry Reding1-0/+3
USB PHYs must have a #phy-cells property, so add one to the Tegra USB PHYs which don't have one. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Tegra132 EMC is not compatible with Tegra124Thierry Reding1-1/+1
The external memory controller found on Tegra132 is not fully compatible with the instantiation on Tegra124, so remove the corresponding string from the list of compatible strings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Use sor0_out clock on Tegra132Thierry Reding1-1/+2
The sor0_out clock is required to make eDP work properly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Do not mark host1x as simple busThierry Reding4-5/+4
The host1x is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Use proper tuple notationThierry Reding5-86/+87
Tuple boundaries should be marked by < and > to make it clear which cells are part of the same tuple. This also helps the json-schema based validation tooling to properly parse this data. While at it, also remove the "immovable" bit from PCI addresses. All of these addresses are in fact "movable". Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-13arm64: tegra: norrin: Add missing panel power supplyThierry Reding1-0/+1
This panel supply is always on, so this does happen to work by accident. Make sure to properly hook up the power supply to model the dependency correctly and so that the panel continues to operate properly even if the supply is not always on. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-13arm64: tegra: Remove simple regulators busThierry Reding9-801/+671
The standard way to do this is to list out the regulators at the top- level. Adopt the standard way to fix validation. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-13arm64: tegra: Remove simple clocks busThierry Reding6-66/+24
The standard way to do this is to list out the clocks at the top-level. Adopt the standard way to fix validation. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-13arm64: tegra: Remove undocumented battery-name propertyThierry Reding2-2/+0
battery-name is not a documented property, so drop it to avoid validation failures. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-13arm64: tegra: Enable XUSB on NorrinThierry Reding2-42/+246
Use the XUSB controller instead of the legacy EHCI controller to enable USB 3.0 support. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Rename sdhci nodes to mmcThierry Reding15-36/+36
The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add unit-address to memory nodeThierry Reding6-6/+6
The memory node requires a unit-address. For some boards the bootloader, which is usually locked down, uses a hard-coded name for the memory node without a unit-address, so we can't fix it on those boards. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Fixup I/O and PLL supply names for HDMI/DPThierry Reding4-8/+8
The I/O and PLL supplies used for HDMI/DP have alternative names. Use the names that are given in the hardware documentation for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Remove parent clock from display controllersThierry Reding2-12/+8
The display controller's parent clock depends on the output that's consuming data from the display controller, so it needs to be specified as the parent of the corresponding output. The device tree bindings do specify this, so just correct the existing device trees that get this wrong. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add interrupt-names for host1xThierry Reding4-0/+4
Interrupt names are used to distinguish between the syncpoint and general host1x interrupts. Make sure they are available in the DT so that drivers can use them if necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add Tegra132 compatible string for host1xThierry Reding1-1/+3
While the host1x controller found on Tegra132 is the same as on Tegra124 it is good practice to also list a SoC-specific compatible string so any SoC-specific quirks can be implemented in drivers if necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add interrupt for Tegra194 memory controllerThierry Reding1-0/+1
This interrupt can be used for the operating system to be interrupted when certain events occur. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Describe interconnect paths on Tegra194Thierry Reding1-0/+70
On Tegra194, all clients of the memory subsystem can generally address 40 bits of system memory. However, bit 39 has special meaning and will cause the memory controller to reorder sectors for block-linear buffer formats. This is primarily useful for graphics-related devices. Use of bit 39 must be controlled on a case-by-case basis. Buffers that are used with bit 39 set by one device may be used with bit 39 cleared by other devices. Care must be taken to allocate buffers at addresses that do not require bit 39 to be set. This is normally not an issue for system memory since there are no Tegra-based systems with enough RAM to exhaust the 39-bit physical address space. However, when a device is behind an IOMMU, such as the ARM SMMU on Tegra194, the IOMMUs input address space can cause IOVA allocations to happen in this region. This is for example the case when an operating system implements a top-down allocation policy for IO virtual addresses. To account for this, describe the path that memory accesses take through the system. Memory clients will send requests to the memory controller, which forwards bits [38:0] of the address either to the external memory controller or the SMMU, depending on the stream ID of the access. A good way to describe this is using the interconnects bindings, see: Documentation/devicetree/bindings/interconnect/interconnect.txt The standard "dma-mem" path is used to describe the path towards system memory via the memory controller. A dma-ranges property in the memory controller's device tree node limits the range of DMA addresses that the memory clients can use to bits [38:0], ensuring that bit 39 is not used. Signed-off-by: Thierry Reding <treding@nvidia.com> --- Changes in v4: - add additional entries for interconnect-names to match interconnects - add EMC as destination for interconnect paths Changes in v3: - add missing interconnect properties for VIC Changes in v2: - use memory client IDs instead of stream IDs (Mikko Perttunen) Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Describe interconnect paths on Tegra186Thierry Reding1-1/+55
The interface used by clients of the memory controller can be configured in a number of different ways. Describe this path using the interconnect bindings to enable the configuration of these parameters. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Remove extra compatible for Tegra210 SDHCIThierry Reding1-4/+4
The SDHCI on Tegra210 is in fact not compatible with the one found on Tegra124. Remove the extra compatible string to reflect that. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Remove extra compatible for Tegra194 SDHCIThierry Reding1-3/+3
The SDHCI on Tegra194 is in fact not compatible with the one found on Tegra186. Remove the extra compatible string to reflect that. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Use standard notation for interruptsThierry Reding1-2/+2
It is customary to use angle brackets around each tuple in the interrupts property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Fix #address-cells/#size-cells for SRAM on Tegra186Thierry Reding1-5/+5
The standard mmio-sram bindings require the #address- and #size-cells properties to be 1. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add missing #phy-cells property on Jetson AGX XavierThierry Reding1-0/+1
PHYs need to have a #phy-cells property that defines how many cells are required in their specifier. The standard Ethernet PHY doesn't require a specifier, so set its #phy-cells to 0. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add missing #phy-cells property on Jetson TX2Thierry Reding1-0/+2
PHYs need to have a #phy-cells property that defines how many cells are required in their specifier. The standard Ethernet PHY doesn't require a specifier, so set its #phy-cells to 0. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-14Linux 5.8-rc1Linus Torvalds1-2/+2
2020-06-14security: Add LSM hooks to set*gid syscallsThomas Cedeno5-1/+40
The SafeSetID LSM uses the security_task_fix_setuid hook to filter set*uid() syscalls according to its configured security policy. In preparation for adding analagous support in the LSM for set*gid() syscalls, we add the requisite hook here. Tested by putting print statements in the security_task_fix_setgid hook and seeing them get hit during kernel boot. Signed-off-by: Thomas Cedeno <thomascedeno@google.com> Signed-off-by: Micah Morton <mortonm@chromium.org>
2020-06-14Revert "btrfs: switch to iomap_dio_rw() for dio"David Sterba4-166/+169
This reverts commit a43a67a2d715540c1368b9501a22b0373b5874c0. This patch reverts the main part of switching direct io implementation to iomap infrastructure. There's a problem in invalidate page that couldn't be solved as regression in this development cycle. The problem occurs when buffered and direct io are mixed, and the ranges overlap. Although this is not recommended, filesystems implement measures or fallbacks to make it somehow work. In this case, fallback to buffered IO would be an option for btrfs (this already happens when direct io is done on compressed data), but the change would be needed in the iomap code, bringing new semantics to other filesystems. Another problem arises when again the buffered and direct ios are mixed, invalidation fails, then -EIO is set on the mapping and fsync will fail, though there's no real error. There have been discussions how to fix that, but revert seems to be the least intrusive option. Link: https://lore.kernel.org/linux-btrfs/20200528192103.xm45qoxqmkw7i5yl@fiona/ Signed-off-by: David Sterba <dsterba@suse.com>
2020-06-13net: ethernet: ti: ale: fix allmulti for nu type aleGrygorii Strashko1-9/+40
On AM65xx MCU CPSW2G NUSS and 66AK2E/L NUSS allmulti setting does not allow unregistered mcast packets to pass. This happens, because ALE VLAN entries on these SoCs do not contain port masks for reg/unreg mcast packets, but instead store indexes of ALE_VLAN_MASK_MUXx_REG registers which intended for store port masks for reg/unreg mcast packets. This path was missed by commit 9d1f6447274f ("net: ethernet: ti: ale: fix seeing unreg mcast packets with promisc and allmulti disabled"). Hence, fix it by taking into account ALE type in cpsw_ale_set_allmulti(). Fixes: 9d1f6447274f ("net: ethernet: ti: ale: fix seeing unreg mcast packets with promisc and allmulti disabled") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-06-13net: ethernet: ti: am65-cpsw-nuss: fix ale parameters initGrygorii Strashko1-1/+1
The ALE parameters structure is created on stack, so it has to be reset before passing to cpsw_ale_create() to avoid garbage values. Fixes: 93a76530316a ("net: ethernet: ti: introduce am65x/j721e gigabit eth subsystem driver") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-06-13net: atm: Remove the error message according to the atomic contextLiao Pingfang1-3/+1
Looking into the context (atomic!) and the error message should be dropped. Signed-off-by: Liao Pingfang <liao.pingfang@zte.com.cn> Signed-off-by: David S. Miller <davem@davemloft.net>