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Update the max MPU voltage range to align with the maximum
possible value allowed in the operating-points table, which is max
target voltage of 132500 uV + 2%.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Message-Id: <20220419143923.25196-1-yegorslists@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* Add comment to improve readability
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-16-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* assign name to gpio line
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-15-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* Update interface pinmux for
- poweroff button
- battery and coincell enable
- ASP and Miraculix
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-14-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* Dispble DMA property of USB1
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-13-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* Add support for uart2 port
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-12-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* Update default brightness and dimming frequency
* Enable current sink, while initialization
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-11-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* Add port to the node lcdc
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-10-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* Update mmcsd voltage regulator node name
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-9-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* Update lable pwm to guardian beeper
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-8-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* update life led label and pin number
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-7-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* MMC presence indicater LED removed from Guardian Board
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-6-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* Disabling poweroff support form RTC will allow poweroff
to handle from other machanism
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-5-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* Add support to guardian mt gpio keypad
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-4-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* Rename label button to power button
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-3-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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* Update partition table to save env and splash image
* GPMC config values optimized for Bosch Guardian Board
* NAND Chip used by Bosch Guardian Board is Micron MT29F4G08ABBFA
Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Message-Id: <20220325100613.1494-2-Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Move some pinmux references to their respective peripherals.
This keeps the pins in safe-mode until they are requested.
Signed-off-by: Adam Ford <aford173@gmail.com>
Message-Id: <20220303171818.11060-2-aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The node name of Ethernet controller should be "ethernet" instead of
"usbether" as required by Ethernet controller devicetree schema:
Documentation/devicetree/bindings/net/ethernet-controller.yaml
This patch can potentially affect boot loaders patching against full
node path instead of using device aliases.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Message-Id: <20220216074927.3619425-8-o.rempel@pengutronix.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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"make dtbs_check":
arch/arm/boot/dts/r9a06g032-rzn1d400-db.dt.yaml: timer: compatible: 'oneOf' conditional failed, one must be fixed:
['arm,cortex-a7-timer', 'arm,armv7-timer'] is too long
'arm,cortex-a7-timer' is not one of ['arm,cortex-a15-timer']
'arm,cortex-a7-timer' is not one of ['arm,armv7-timer']
'arm,cortex-a7-timer' is not one of ['arm,armv8-timer']
From schema: Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
The Cortex-A7 timer should just declare compatibility with
"arm,armv7-timer".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a8e0cf00a983b4c539cdb1cfad5cc6b10b423c5b.1649680220.git.geert+renesas@glider.be
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Add device nodes for the General Purpose Input/Output (GPIO) blocks on
the Renesas R-Car S4-8 (R8A779F0) SoC.
Note that GPIO blocks 4-7 are not added, as they can only be accessed
from the Control Domain.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7fb68561026fa8bb5d9baf0596560c5c719a38cc.1649086225.git.geert+renesas@glider.be
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This adds the PN544 NFC chip mounted on some of the Codina models
numbered GT-I8160P. The "P" at the end of the product number
indicates that an NFC chip is mounted.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Enable Ethernet{0,1} interfaces on RZ/G2UL SMARC EVK.
Ethernet0 pins are muxed with CAN0, CAN1, SSI1 and RSPI1 pins and Ethernet0
device selection is based on the SW1[3] switch position.
Set SW1[3] to position OFF for selecting CAN0, CAN1, SSI1 and RSPI1.
Set SW1[3] to position ON for selecting Ethernet0.
This patch disables Ethernet0 on RZ/G2UL SMARC platform by default.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402081328.26292-8-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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RZ/G2UL SoM has both 64GB eMMC and microSD connected to SDHI0.
Both these interfaces are mutually exclusive and the SD0 device
selection is based on SW1[2] on SoM module.
Set SW1[2] to position OFF for selecting eMMC
Set SW1[2] to position ON for selecting microSD
This patch enables eMMC on RZ/G2UL SMARC platform by default.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402081328.26292-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Enable the microSD card slot connected to SDHI1 on the RZ/G2UL SMARC
platform by removing the sdhi1 override which disabled it, and by adding
the necessary pinmux required for SDHI1.
This patch also adds gpios property to vccq_sdhi1 regulator.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402081328.26292-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add Gigabit Ethernet{0,1} nodes to SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402081328.26292-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402081328.26292-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add scif0 and audio clk pins to soc pinctrl dtsi and drop deleting
the pinctrl-0 and pinctrl-names properties for scif0 node so that
we now actually make use of these properties for scif0.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402081328.26292-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Fillup the pinctrl(GPIO) stub node in RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402081328.26292-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11):
- memory
- External input clock
- CPG
- DMA
- SCIF
It shares the same carrier board with RZ/G2L, but the pin mapping is
different. Disable the device nodes which are not tested and delete the
corresponding pinctrl definitions.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220412161314.13800-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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