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2020-10-20PCI: dwc: Add link up check in dw_child_pcie_ops.map_bus()Hou Zhiqiang1-0/+11
NXP Layerscape (ls1028a, ls2088a), dra7xxx and imx6 platforms are either programmed or statically configured to forward the error triggered by a link-down state (eg no connected endpoint device) on the system bus for PCI configuration transactions; these errors are reported as an SError at system level, which is fatal. Enumerating a PCI tree when the PCIe link is down is not sensible either, so even if the link-up check is racy (link can go down after map_bus() is called) add a link-up check in map_bus() to prevent issuing configuration transactions when the link is down. SError report: SError Interrupt on CPU2, code 0xbf000002 -- SError CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67 Hardware name: LS1046A RDB Board (DT) pstate: 20000085 (nzCv daIf -PAN -UAO BTYPE=--) pc : pci_generic_config_read+0x3c/0xe0 lr : pci_generic_config_read+0x24/0xe0 sp : ffff80001003b7b0 x29: ffff80001003b7b0 x28: ffff80001003ba74 x27: ffff000971d96800 x26: ffff00096e77e0a8 x25: ffff80001003b874 x24: ffff80001003b924 x23: 0000000000000004 x22: 0000000000000000 x21: 0000000000000000 x20: ffff80001003b874 x19: 0000000000000004 x18: ffffffffffffffff x17: 00000000000000c0 x16: fffffe0025981840 x15: ffffb94c75b69948 x14: 62203a383634203a x13: 666e6f635f726568 x12: 202c31203d207265 x11: 626d756e3e2d7375 x10: 656877202c307830 x9 : 203d206e66766564 x8 : 0000000000000908 x7 : 0000000000000908 x6 : ffff800010900000 x5 : ffff00096e77e080 x4 : 0000000000000000 x3 : 0000000000000003 x2 : 84fa3440ff7e7000 x1 : 0000000000000000 x0 : ffff800010034000 Kernel panic - not syncing: Asynchronous SError Interrupt CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67 Hardware name: LS1046A RDB Board (DT) Call trace: dump_backtrace+0x0/0x1c0 show_stack+0x18/0x28 dump_stack+0xd8/0x134 panic+0x180/0x398 add_taint+0x0/0xb0 arm64_serror_panic+0x78/0x88 do_serror+0x68/0x180 el1_error+0x84/0x100 pci_generic_config_read+0x3c/0xe0 dw_pcie_rd_other_conf+0x78/0x110 pci_bus_read_config_dword+0x88/0xe8 pci_bus_generic_read_dev_vendor_id+0x30/0x1b0 pci_bus_read_dev_vendor_id+0x4c/0x78 pci_scan_single_device+0x80/0x100 Link: https://lore.kernel.org/r/20200916054130.8685-1-Zhiqiang.Hou@nxp.com Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [lorenzo.pieralisi@arm.com: rewrote the commit log, remove Fixes tag] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-10-16PCI/ASPM: Remove struct pcie_link_state.l1ssSaheed O. Bolarinwa2-35/+50
Previously we computed L1.2 parameters in the enumeration path, saved them in struct pcie_link_state.l1ss, and programmed them into the devices whenever we enabled or disabled L1.2 on the link. But these parameters are constant and don't need to be updated when enabling/disabling L1.2. Compute and program the L1.2 parameters once during enumeration and remove the struct pcie_link_state.l1ss member. No functional change intended. [bhelgaas: rework to program L1.2 parameters during enumeration] Link: https://lore.kernel.org/r/20201015193039.12585-13-helgaas@kernel.org Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-10-16PCI/ASPM: Remove struct aspm_register_info.l1ss_capSaheed O. Bolarinwa1-32/+21
Previously we stored the L1SS Capabilities value in the struct aspm_register_info. We only need this information in one place, so read it there and remove struct aspm_register_info completely, since it's now empty. No functional change intended. [bhelgaas: split up, don't cache l1ss_cap in pci_dev] Link: https://lore.kernel.org/r/20201015193039.12585-12-helgaas@kernel.org Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-10-16PCI/ASPM: Pass L1SS Capabilities value, not struct aspm_register_infoBjorn Helgaas1-9/+8
aspm_calc_l1ss_info() needs only the L1SS Capabilities. It doesn't need anything else from struct aspm_register_info, so pass only the Capabilities value. No functional change intended. Link: https://lore.kernel.org/r/20201015193039.12585-11-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-10-16PCI/ASPM: Remove struct aspm_register_info.l1ss_ctl1Saheed O. Bolarinwa1-12/+14
Previously we stored the L1SS Control 1 register in the struct aspm_register_info. We only need this information in one place, so read it there and remove it from struct aspm_register_info. No functional change intended. [bhelgaas: split ctl1/ctl2] Link: https://lore.kernel.org/r/20201015193039.12585-10-helgaas@kernel.org Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-10-16PCI/ASPM: Remove struct aspm_register_info.l1ss_ctl2 (unused)Bjorn Helgaas1-4/+1
We never use the aspm_register_info.l1ss_ctl2 value, so remove it. No functional change intended. Link: https://lore.kernel.org/r/20201015193039.12585-9-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-10-16PCI/ASPM: Remove struct aspm_register_info.l1ss_cap_ptrSaheed O. Bolarinwa3-21/+19
Save the L1 Substates Capability pointer in struct pci_dev. Then we don't have to keep track of it in the struct aspm_register_info and struct pcie_link_state, which makes the code easier to read. No functional change intended. [bhelgaas: split to a separate patch] Link: https://lore.kernel.org/r/20201015193039.12585-8-helgaas@kernel.org Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-10-16PCI/ASPM: Remove struct aspm_register_info.latency_encodingSaheed O. Bolarinwa1-14/+10
Previously we stored L0s and L1 Exit Latency information from the Link Capabilities register in the struct aspm_register_info. We only need these latencies when we already have the Link Capabilities values, so use those directly and remove the latencies from struct aspm_register_info. No functional change intended. Link: https://lore.kernel.org/r/20201015193039.12585-7-helgaas@kernel.org Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-10-16PCI/ASPM: Remove struct aspm_register_info.enabledSaheed O. Bolarinwa1-8/+6
Previously we stored the "ASPM Control" bits from the Link Control register in the struct aspm_register_info. Read PCI_EXP_LNKCTL directly when needed. This means we can use the PCI_EXP_LNKCTL_ASPM_* bits directly instead of the similar but different PCIE_LINK_STATE_* bits. No functional change intended. [bhelgaas: drop get_aspm_enable() and read LNKCTL once directly] Link: https://lore.kernel.org/r/20201015193039.12585-6-helgaas@kernel.org Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-10-16PCI/ASPM: Remove struct aspm_register_info.supportSaheed O. Bolarinwa2-11/+16
Previously we stored the "ASPM Support" field from the Link Capabilities register in the struct aspm_register_info. Read the Link Capabilities directly when needed and remove it from the struct aspm_register_info. No functional change intended. [bhelgaas: remove pci_dev cached copy since LNKCAP isn't truly read-only, add PCI_EXP_LNKCAP_ASPM_L0S & PCI_EXP_LNKCAP_ASPM_L1, check them directly instead of adding aspm_support()] Link: https://lore.kernel.org/r/20201015193039.12585-5-helgaas@kernel.org Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-10-16PCI/ASPM: Use 'parent' and 'child' for readabilityBjorn Helgaas1-4/+5
Other users of link->pdev and link->downstream, e.g., pcie_aspm_cap_init(), pcie_config_aspm_l1ss(), and pcie_config_aspm_link(), use "parent" and "child" as local names. Do the same in aspm_calc_l1ss_info() for readability. No functional change intended. Link: https://lore.kernel.org/r/20201015193039.12585-4-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-10-16PCI/ASPM: Move LTR path check to where it's usedBjorn Helgaas1-9/+8
pcie_get_aspm_reg() mostly reads ASPM-related registers, but in some cases it also updates the value read from PCI_L1SS_CAP based on LTR properties. Move this update to the point where the value is used to make the code more readable. No functional change intended, although previously we could clear PCI_L1SS_CAP_ASPM_L1_2 for both ends of the link, and now we'll only do it for the downstream end of a link. This shouldn't matter because we always test that bit by ANDing l1ss_cap for the upstream and downstream ends. Link: https://lore.kernel.org/r/20201015193039.12585-3-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-10-16PCI/ASPM: Move pci_clear_and_set_dword() earlierBjorn Helgaas1-11/+11
Move pci_clear_and_set_dword() earlier in file to prepare for future patch. No functional change intended. Link: https://lore.kernel.org/r/20201015193039.12585-2-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-10-13PCI: dwc: Fix MSI page leakage in suspend/resumeJisheng Zhang3-17/+36
Currently, dw_pcie_msi_init() allocates and maps page for msi, then program the PCIE_MSI_ADDR_LO and PCIE_MSI_ADDR_HI. The Root Complex may lose power during suspend-to-RAM, so when we resume, we want to redo the latter but not the former. If designware based driver (for example, pcie-tegra194.c) calls dw_pcie_msi_init() in resume path, the msi page will be leaked. As pointed out by Rob and Ard, there's no need to allocate a page for the MSI address, we could use an address in the driver data. To avoid map the MSI msg again during resume, we move the map MSI msg from dw_pcie_msi_init() to dw_pcie_host_init(). Suggested-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201009155505.5a580ef5@xhacker.debian Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-10-13PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabledJisheng Zhang1-1/+1
If MSI is disabled, there's no need to program PCIE_MSI_INTR0_MASK and PCIE_MSI_INTR0_ENABLE registers. Link: https://lore.kernel.org/r/20201009155436.27e67238@xhacker.debian Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2020-10-13PCI: keystone: Remove iATU register mappingKunihiko Hayashi1-16/+4
After applying "PCI: dwc: Add common iATU register support", there is no need to set own iATU in the Keystone driver itself. Suggested-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1601444167-11316-5-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2020-10-13PCI: dwc: Add common iATU register supportKunihiko Hayashi1-0/+5
This gets iATU register area from reg property that has reg-names "atu". In Synopsys DWC version 4.80 or later, since iATU register area is separated from core register area, this area is necessary to get from DT independently. Suggested-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1601444167-11316-4-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2020-10-13dt-bindings: PCI: uniphier-ep: Add iATU register descriptionKunihiko Hayashi1-6/+14
In the dt-bindings, "atu" reg-names is required to get the register space for iATU in Synopsis DWC version 4.80 or later. Link: https://lore.kernel.org/r/1601444167-11316-3-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-10-13dt-bindings: PCI: uniphier: Add iATU register descriptionKunihiko Hayashi1-0/+1
In the dt-bindings, "atu" reg-names is required to get the register space for iATU in Synopsys DWC version 4.80 or later. Link: https://lore.kernel.org/r/1601444167-11316-2-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Rob Herring <robh@kernel.org>
2020-10-05asm-generic/io.h: Fix !CONFIG_GENERIC_IOMAP pci_iounmap() implementationLorenzo Pieralisi1-12/+27
For arches that do not select CONFIG_GENERIC_IOMAP, the current pci_iounmap() function does nothing causing obvious memory leaks for mapped regions that are backed by MMIO physical space. In order to detect if a mapped pointer is IO vs MMIO, a check must made available to the pci_iounmap() function so that it can actually detect whether the pointer has to be unmapped. In configurations where CONFIG_HAS_IOPORT_MAP && !CONFIG_GENERIC_IOMAP, a mapped port is detected using an ioport_map() stub defined in asm-generic/io.h. Use the same logic to implement a stub (ie __pci_ioport_unmap()) that detects if the passed in pointer in pci_iounmap() is IO vs MMIO to iounmap conditionally and call it in pci_iounmap() fixing the issue. Leave __pci_ioport_unmap() as a NOP for all other config options. Tested-by: George Cherian <george.cherian@marvell.com> Link: https://lore.kernel.org/lkml/20200905024811.74701-1-yangyingliang@huawei.com Link: https://lore.kernel.org/lkml/20200824132046.3114383-1-george.cherian@marvell.com Link: https://lore.kernel.org/r/a9daf8d8444d0ebd00bc6d64e336ec49dbb50784.1600254147.git.lorenzo.pieralisi@arm.com Reported-by: George Cherian <george.cherian@marvell.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: George Cherian <george.cherian@marvell.com> Cc: Will Deacon <will@kernel.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Yang Yingliang <yangyingliang@huawei.com>
2020-10-05sparc32: Move ioremap/iounmap declaration before asm-generic/io.h includeLorenzo Pieralisi1-6/+7
Move the ioremap/iounmap declaration before asm-generic/io.h is included so that it is visible within it. Link: https://lore.kernel.org/r/93e2f23cda474a92a4708d4c50c9c359426a2162.1600254147.git.lorenzo.pieralisi@arm.com Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: "David S. Miller" <davem@davemloft.net> Cc: "David S. Miller" <davem@davemloft.net>
2020-10-05sparc32: Remove useless io_32.h __KERNEL__ preprocessor guardLorenzo Pieralisi1-4/+0
The __KERNEL_ preprocessor guard is useless in non-uapi headers. Remove it. Link: https://lore.kernel.org/r/084753d3064fe946ff1963eda2eb425cfd7daa7b.1600254147.git.lorenzo.pieralisi@arm.com Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: David S. Miller <davem@davemloft.net> Cc: David S. Miller <davem@davemloft.net>
2020-10-02PCI: aardvark: Fix initialization with old Marvell's Arm Trusted FirmwarePali Rohár1-1/+3
Old ATF automatically power on pcie phy and does not provide SMC call for phy power on functionality which leads to aardvark initialization failure: [ 0.330134] mvebu-a3700-comphy d0018300.phy: unsupported SMC call, try updating your firmware [ 0.338846] phy phy-d0018300.phy.1: phy poweron failed --> -95 [ 0.344753] advk-pcie d0070000.pcie: Failed to initialize PHY (-95) [ 0.351160] advk-pcie: probe of d0070000.pcie failed with error -95 This patch fixes above failure by ignoring 'not supported' error in aardvark driver. In this case it is expected that phy is already power on. Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Link: https://lore.kernel.org/r/20200902144344.16684-3-pali@kernel.org Fixes: 366697018c9a ("PCI: aardvark: Add PHY support") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Cc: <stable@vger.kernel.org> # 5.8+: ea17a0f153af: phy: marvell: comphy: Convert internal SMCC firmware return codes to errno
2020-10-02phy: marvell: comphy: Convert internal SMCC firmware return codes to errnoPali Rohár2-6/+22
Driver ->power_on and ->power_off callbacks leaks internal SMCC firmware return codes to phy caller. This patch converts SMCC error codes to standard linux errno codes. Include file linux/arm-smccc.h already provides defines for SMCC error codes, so use them instead of custom driver defines. Note that return value is signed 32bit, but stored in unsigned long type with zero padding. Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Link: https://lore.kernel.org/r/20200902144344.16684-2-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-10-02PCI: cadence: Simplify cdns_pcie_host_init_address_translation() return expressionQinglang Miao1-6/+2
Simplify the return expression. Link: https://lore.kernel.org/r/20200921131053.92752-1-miaoqinglang@huawei.com Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-10-02PCI: brcmstb: Add bcm7211, bcm7216, bcm7445, bcm7278 to match listJim Quinlan1-0/+4
Now that the support is in place with previous commits, we add several chips that use the BrcmSTB driver. Link: https://lore.kernel.org/r/20200911175232.19016-11-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Rob Herring <robh@kernel.org>
2020-10-02PCI: brcmstb: Set bus max burst size by chip typeJim Quinlan1-4/+15
The proper value of the parameter SCB_MAX_BURST_SIZE varies per chip. The 2711 family requires 128B whereas other devices can employ 512. The assignment is complicated by the fact that the values for this two-bit field have different meanings; Value Type_Generic Type_7278 00 Reserved 128B 01 128B 256B 10 256B 512B 11 512B Reserved Link: https://lore.kernel.org/r/20200911175232.19016-10-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <jquinlan@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2020-10-02PCI: brcmstb: Accommodate MSI for older chipsJim Quinlan1-21/+49
Older BrcmSTB chips do not have a separate register for MSI interrupts; the MSIs are in a register that also contains unrelated interrupts. In addition, the interrupts lie in bits [31..24] for these legacy chips. This commit provides common code for both legacy and non-legacy MSI interrupt registers. Link: https://lore.kernel.org/r/20200911175232.19016-9-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <jquinlan@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2020-10-02PCI: brcmstb: Set additional internal memory DMA viewport sizesJim Quinlan1-18/+49
The Raspberry Pi (RPI) is currently the only chip using this driver (pcie-brcmstb.c). There, only one memory controller is used, without an extension region, and the SCB0 viewport size is set to the size of the first and only dma-range region. Other BrcmSTB SOCs have more complicated memory configurations that require setting additional viewport sizes. BrcmSTB PCIe controllers are intimately connected to the memory controller(s) on the SOC. The SOC may have one to three memory controllers; they are indicated by the term SCBi. Each controller has a base region and an optional extension region. In physical memory, the base and extension regions of a controller are not adjacent, but in PCIe-space they are. There is a "viewport" for each memory controller that allows DMA from endpoint devices. Each viewport's size must be set to a power of two, and that size must be equal to or larger than the amount of memory each controller supports which is the sum of base region and its optional extension. Further, the 1-3 viewports are also adjacent in PCIe-space. Unfortunately the viewport sizes cannot be ascertained from the "dma-ranges" property so they have their own property, "brcm,scb-sizes". This is because dma-range information does not indicate what memory controller it is associated. For example, consider the following case where the size of one dma-range is 2GB and the second dma-range is 1GB: /* Case 1: SCB0 size set to 4GB */ dma-range0: 2GB (from memc0-base) dma-range1: 1GB (from memc0-extension) /* Case 2: SCB0 size set to 2GB, SCB1 size set to 1GB */ dma-range0: 2GB (from memc0-base) dma-range1: 1GB (from memc0-extension) By just looking at the dma-ranges information, one cannot tell which situation applies. That is why an additional property is needed. Its length indicates the number of memory controllers being used and each value indicates the viewport size. Note that the RPI DT does not have a "brcm,scb-sizes" property value, as it is assumed that it only requires one memory controller and no extension. So the optional use of "brcm,scb-sizes" will be backwards compatible. One last layer of complexity exists: all of the viewports sizes must be added and rounded up to a power of two to determine what the "BAR" size is. Further, an offset must be given that indicates the base PCIe address of this "BAR". The use of the term BAR is typically associated with endpoint devices, and the term is used here because the PCIe HW may be used as an RC or an EP. In the former case, all of the system memory appears in a single "BAR" region in PCIe memory. As it turns out, BrcmSTB PCIe HW is rarely used in the EP role and its system of mapping memory is an artifact that requires multiple dma-ranges regions. Link: https://lore.kernel.org/r/20200911175232.19016-8-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2020-10-02PCI: brcmstb: Add control of rescal resetJim Quinlan1-2/+77
Some STB chips have a special purpose reset controller named RESCAL (reset calibration). The PCIe HW can now control RESCAL to start and stop its operation. On probe(), the RESCAL is deasserted and the driver goes through the sequence of setting registers and reading status in order to start the internal PHY that is required for the PCIe. Link: https://lore.kernel.org/r/20200911175232.19016-7-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <jquinlan@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-30PCI: Add Kconfig options for MPS/MRRS strategyJim Quinlan2-0/+74
Add Kconfig options for changing the default pcie_bus_config, i.e., the strategy for configuration MPS and MRRS, in the same manner as the CONFIG_PCIEASPM_XXXX choice. The pci_bus_config setting may still be overridden by kernel command-line parameters, e.g., "pci=pcie_bus_tune_off". [bhelgaas: depend on EXPERT, tweak help texts] Link: https://lore.kernel.org/r/20200928194651.5393-2-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-09-30PCI/PM: Revert "PCI/PM: Apply D2 delay as milliseconds, not microseconds"Bjorn Helgaas2-4/+4
This reverts commit 7e24bc347e57992d532bc2ed700209b0fc0a4bf5. 7e24bc347e57 was based on PCIe r5.0, sec 5.9, which claims we need a 200 ms delay when transitioning to or from D2. However, sec 5.3.1.3 states the delay as 200 μs (microseconds), as does the table in PCIe r4.0, sec 5.9.1. This looks like a typo in the r5.0 spec, so revert back to a 200 μs delay instead of a 200 ms delay. Fixes: 7e24bc347e57 ("PCI/PM: Apply D2 delay as milliseconds, not microseconds") Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2020-09-30PCI/PM: Remove unused PCI_PM_BUS_WAITBjorn Helgaas1-1/+0
476e7faefc43 ("PCI PM: Do not wait for buses in B2 or B3 during resume") removed the last use of PCI_PM_BUS_WAIT. Remove the definition as well. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2020-09-30PCI/P2PDMA: Drop double zeroing for sg_init_table()Julia Lawall1-1/+1
sg_init_table() zeroes its first argument, so the allocation of that argument doesn't have to. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression x; @@ x = - kzalloc + kmalloc (...) ... sg_init_table(x,...) // </smpl> Link: https://lore.kernel.org/r/1600601186-7420-15-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-09-30PCI: Simplify bool comparisonsKrzysztof Wilczyński1-2/+2
Take care about Coccinelle warnings: drivers/pci/pci.c:6008:6-12: WARNING: Comparison to bool drivers/pci/pci.c:6024:7-13: WARNING: Comparison to bool No change to functionality intended. Link: https://lore.kernel.org/r/20200925224555.1752460-1-kw@linux.com Signed-off-by: Krzysztof Wilczyński <kw@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-09-29PCI/PM: Rename pci_dev.d3_delay to d3hot_delayKrzysztof Wilczyński12-54/+54
PCI devices support two variants of the D3 power state: D3hot (main power present) D3cold (main power removed). Previously struct pci_dev contained: unsigned int d3_delay; /* D3->D0 transition time in ms */ unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ "d3_delay" refers specifically to the D3hot state. Rename it to "d3hot_delay" to avoid ambiguity and align with the ACPI "_DSM for Specifying Device Readiness Durations" in the PCI Firmware spec r3.2, sec 4.6.9. There is no change to the functionality. Link: https://lore.kernel.org/r/20200730210848.1578826-1-kw@linux.com Signed-off-by: Krzysztof Wilczyński <kw@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-09-29PCI/PM: Remove unused pcibios_pm_opsVaibhav Gupta2-30/+0
The "struct dev_pm_ops pcibios_pm_ops", declared in include/linux/pci.h and defined in drivers/pci/pci-driver.c, provided arch-specific hooks when a PCI device was doing a hibernate transition. 394216275c7d ("s390: remove broken hibernate / power management support") removed the last use of pcibios_pm_ops, so remove it completely. [bhelgaas: drop unused "error"] Link: https://lore.kernel.org/r/20200730194416.1029509-1-vaibhavgupta40@gmail.com Reported-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Vaibhav Gupta <vaibhavgupta40@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-09-28PCI: shpchp: Remove unused 'rc' assignmentKrzysztof Wilczyński1-1/+0
The value of the constant POWER_FAILURE assigned to the variable rc after the power fault check is never used for anything, so remove it. Addresses-Coverity-ID: 1226899 ("Unused value") Link: https://lore.kernel.org/r/20200923025225.471459-1-kw@linux.com Signed-off-by: Krzysztof Wilczyński <kw@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-09-28PCI: dwc: Fix 'cast truncates bits from constant value'Gustavo Pimentel1-1/+1
Fixes warning given by executing "make C=2 drivers/pci/" Sparse output: CHECK drivers/pci/controller/dwc/pcie-designware.c drivers/pci/controller/dwc/pcie-designware.c:432:52: warning: cast truncates bits from constant value (ffffffff7fffffff becomes 7fffffff) Link: https://lore.kernel.org/r/7ea7f7d342f97c758949a17b870012f52ce5b3f5.1600767645.git.gustavo.pimentel@synopsys.com Reported-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Joao Pinto <jpinto@synopsys.com>
2020-09-24misc: pci_endpoint_test: Add driver data for Layerscape PCIe controllersHou Zhiqiang1-2/+6
The commit 0a121f9bc3f5 ("misc: pci_endpoint_test: Use streaming DMA APIs for buffer allocation") changed to use streaming DMA APIs, however, dma_map_single() might not return a 4KB aligned address, so add the default_data as driver data for Layerscape PCIe controllers to make it 4KB aligned. Link: https://lore.kernel.org/r/20200918080024.13639-13-Zhiqiang.Hou@nxp.com Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Rob Herring <robh@kernel.org>
2020-09-24misc: pci_endpoint_test: Add LS1088a in pci_device_id tableXiaowei Bao1-0/+2
Add LS1088a in pci_device_id table so that pci-epf-test can be used for testing PCIe EP in LS1088a. Link: https://lore.kernel.org/r/20200918080024.13639-12-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2020-09-21PCI: layerscape: Add EP mode support for ls1088a and ls2088aXiaowei Bao1-19/+53
Add PCIe EP mode support for ls1088a and ls2088a, there are some difference between LS1 and LS2 platform, so refactor the code of the EP driver. Link: https://lore.kernel.org/r/20200918080024.13639-10-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-09-21PCI: layerscape: Modify the MSIX to the doorbell modeXiaowei Bao1-1/+2
dw_pcie_ep_raise_msix_irq was never called in the exisitng driver before, because the ls1046a platform don't support the MSIX feature and msix_capable was always set to false. Now that add the ls1088a platform with MSIX support, use the doorbell method to support the MSIX feature. Link: https://lore.kernel.org/r/20200918080024.13639-9-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2020-09-21PCI: layerscape: Modify the way of getting capability with different PEXXiaowei Bao1-8/+23
The different PCIe controller in one board may be have different capability of MSI or MSIX, so change the way of getting the MSI capability, make it more flexible. Link: https://lore.kernel.org/r/20200918080024.13639-8-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-09-21PCI: layerscape: Fix some format issue of the codeXiaowei Bao1-2/+2
Fix some format issue of the code in EP driver. Link: https://lore.kernel.org/r/20200918080024.13639-7-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2020-09-21dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088aXiaowei Bao1-0/+2
Add compatible strings for ls1088a and ls2088a. Link: https://lore.kernel.org/r/20200918080024.13639-6-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Rob Herring <robh@kernel.org>
2020-09-21PCI: designware-ep: Modify MSI and MSIX CAP way of findingXiaowei Bao2-21/+118
Each PF of EP device should have its own MSI or MSIX capabitily struct, so create a dw_pcie_ep_func struct and move the msi_cap and msix_cap to this struct from dw_pcie_ep, and manage the PFs via a list. Link: https://lore.kernel.org/r/20200918080024.13639-5-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-09-21PCI: designware-ep: Move the function of getting MSI capability forwardXiaowei Bao1-4/+4
Move the function of getting MSI capability to the front of init function, because the init function of the EP platform driver will use the return value by the function of getting MSI capability. Link: https://lore.kernel.org/r/20200918080024.13639-4-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2020-09-21PCI: designware-ep: Add the doorbell mode of MSI-X in EP modeXiaowei Bao2-0/+31
Add the doorbell mode of MSI-X in DWC EP driver. Link: https://lore.kernel.org/r/20200918080024.13639-3-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2020-09-21PCI: designware-ep: Add multiple PFs support for DWCXiaowei Bao3-59/+143
Add multiple PFs support for DWC, due to different PF have different config space, we use func_conf_select callback function to access the different PF's config space, the different chip company need to implement this callback function when use the DWC IP core and intend to support multiple PFs feature. Link: https://lore.kernel.org/r/20200918080024.13639-2-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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