linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2021-03-29	arm64: dts: ls1028a: set up the real link speed for ENETC port 2	Vladimir Oltean	1	-1/+1
	In NXP LS1028A there is a MAC-to-MAC internal link between enetc_port2 and mscc_felix_port4. This link operates at 2.5Gbps and is described as such for the mscc_felix_port4 node. The reason for the discrepancy is a limitation in the PHY library support for fixed-link nodes. Due to the fact that the PHY library registers a software PHY which emulates the clause 22 register map, the drivers/net/phy/fixed_phy.c driver only supports speeds up to 1Gbps. The mscc_felix_port4 node is probed by DSA, which does not use the PHY library directly, but phylink, and phylink has a different representation for fixed-link nodes, one that does not have the limitation of not being able to represent speeds > 1Gbps. Since the enetc driver was converted to phylink too as of commit 71b77a7a27a3 ("enetc: Migrate to PHYLINK and PCS_LYNX"), the limitation has been practically lifted there too, and we can describe the real link speed in the device tree now. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29	arm64: dts: imx8mm-nitrogen-r2: add ecspi2 support	Adrien Grassein	1	-0/+20
	Add the description for ecspi2 support. Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-03-29	arm64: dts: imx: add imx8qm mek support	Dong Aisheng	2	-0/+145
	The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53 proccessor with powerful graphic and multimedia features. This patch adds i.MX8QuadMax MEK board support. Note that MX8QM needs a special workaround for TLB flush due to a SoC errata, otherwise there may be random crash if enable both clusters of A72 and A53. As the errata workaround is still not in mainline, so we disable A72 cluster first for MX8QM MEK. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>