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2020-06-25ARM: tegra: Use numeric unit-addressesThierry Reding1-1/+1
Unit-addresses should be numeric. This fixes a validation failure seen using the json-schema tooling. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: medcom-wide: Remove extra panel power supplyThierry Reding1-1/+1
Simple panels can only have a single power supply. The second listed supply is not needed because it is also the input supply of the first supply and therefore will always be on at the same time. In retrospect the panel probably doesn't qualify as simple since it apparently does need both of these supplies, even if in the case of the Medcom Wide it isn't necessary to explicitly hook them up. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Use proper unit-addresses for OPPsThierry Reding4-496/+496
Use commas rather than underscores to separate the various parts of the unit-address in CPU OPPs to make them properly validate under the json- schema bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add missing clock-names for SDHCI controllersThierry Reding3-0/+12
The Tegra SDHCI controllers need to have a clock-names property according to the bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Fix order of XUSB controller clocksThierry Reding1-2/+2
This is purely to make the json-schema validation tools happy because they cannot deal with string arrays that may be in arbitrary order. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add #reset-cells to Tegra124 memory controllerThierry Reding1-0/+1
The memory controller exposes a set of memory client resets and needs to specify the #reset-cells property in order to advertise the number of cells needed to describe each of the resets. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add missing panel power suppliesThierry Reding3-1/+3
Both Nyan boards as well as Venice2 are missing panel power supplies. Add them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add micro-USB A/B port on Jetson TK1Thierry Reding1-0/+6
Run the micro-USB A/B port on Jetson TK1 in host mode by default. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Use proper tuple notationThierry Reding5-82/+89
Tuple boundaries should be marked by < and > to make it clear which cells are part of the same tuple. This also helps the json-schema based validation tooling to properly parse this data. While at it, also remove the "immovable" bit from PCI addresses. All of these addresses are in fact "movable". Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Use standard name for Ethernet devicesThierry Reding4-4/+4
Ethernet device should be named "ethernet@<unit-address>". Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add missing #sound-dai-cells property to codecsThierry Reding5-0/+5
Audio codecs need a #sound-dai-cells property, so add one to the audio codecs on various Tegra-based boards that don't have one. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add missing #phy-cells property to USB PHYsThierry Reding4-0/+11
USB PHYs must have a #phy-cells property, so add one to the Tegra USB PHYs which don't have one. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Tegra114 SDHCI is not backwards-compatibleThierry Reding1-4/+4
The SDHCI controller instantiated on Tegra114 is not backwards- compatible with the version on Tegra30, so remove the corresponding compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Rename sdhci nodes to mmcThierry Reding33-64/+64
The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Drop display controller parent clocks on Tegra124Thierry Reding1-6/+4
The parent clocks are determined by the output that will be used, not by the display controller that drives the output. On previous generations a simple RGB output used to be part of the display controller and hence an explicit parent clock needed to be assigned to the display controller to drive the RGB output. Starting with Tegra124, that RGB output has been dropped and the parent clock can therefore be removed from the display controller device tree nodes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23ARM: tegra: The Tegra114 DC is not backwards-compatibleThierry Reding1-2/+2
The display controller on Tegra114 is in fact not backwards-compatible with the instantiation found on earlier SoCs. Drop the misleading compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23ARM: tegra: gr3d is not backwards-compatibleThierry Reding1-1/+1
The instantiation of gr3d in Tegra114 is not backwards-compatible with the version found on earlier chips. Remove the misleading compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23ARM: tegra: gr2d is not backwards-compatibleThierry Reding1-1/+1
The instantiation of gr2d in Tegra114 is not backwards-compatible with the version found on earlier chips. While the hardware IP is identical, the compatible string also describes the integration of the IP, which in the case of Tegra114 is slightly different in that it's part of the HEG power partition, whereas it wasn't previously. Drop the misleading compatible string so that drivers that support the older integrations cannot match on it. Since they wouldn't be able to control the power partition, such driver wouldn't be able to access any of the registers of the IP. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23ARM: tegra: Add missing host1x propertiesThierry Reding4-0/+8
The host1x device tree bindings require the clock- and interrupt-names properties to be present, so add them where missing. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23ARM: tegra: Do not mark host1x as simple busThierry Reding4-4/+4
The host1x is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23ARM: tegra: tn7: Use the correct DSI/CSI supplyThierry Reding1-1/+1
The correct DSI/CSI supply property is called vdd-dsi-csi-supply, so use that instead of the wrong vdd-supply property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23ARM: tegra: roth: Use the correct DSI/CSI supplyThierry Reding1-1/+1
The correct DSI/CSI supply property is called vdd-dsi-csi-supply, so use that instead of the wrong vdd-supply property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23ARM: tegra: Remove battery-name propertyThierry Reding1-1/+0
This property is not documented and will cause a validation failure. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23ARM: tegra: Remove simple regulators busThierry Reding19-1353/+1122
The standard way to do this is to list out the regulators at the top level. Adopt the standard way to fix validation. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23ARM: tegra: Remove simple clocks busThierry Reding14-154/+56
The standard way to do this is to list out the clocks at the top-level. Adopt the standard way to fix validation. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23ARM: tegra: Add missing clock-names for SDHCI on Tegra114Thierry Reding1-0/+4
The Tegra SDHCI controller bindings state that the clock-names property is required, so add the missing properties on Tegra114. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-14Linux 5.8-rc1Linus Torvalds1-2/+2
2020-06-14security: Add LSM hooks to set*gid syscallsThomas Cedeno5-1/+40
The SafeSetID LSM uses the security_task_fix_setuid hook to filter set*uid() syscalls according to its configured security policy. In preparation for adding analagous support in the LSM for set*gid() syscalls, we add the requisite hook here. Tested by putting print statements in the security_task_fix_setgid hook and seeing them get hit during kernel boot. Signed-off-by: Thomas Cedeno <thomascedeno@google.com> Signed-off-by: Micah Morton <mortonm@chromium.org>
2020-06-14Revert "btrfs: switch to iomap_dio_rw() for dio"David Sterba4-166/+169
This reverts commit a43a67a2d715540c1368b9501a22b0373b5874c0. This patch reverts the main part of switching direct io implementation to iomap infrastructure. There's a problem in invalidate page that couldn't be solved as regression in this development cycle. The problem occurs when buffered and direct io are mixed, and the ranges overlap. Although this is not recommended, filesystems implement measures or fallbacks to make it somehow work. In this case, fallback to buffered IO would be an option for btrfs (this already happens when direct io is done on compressed data), but the change would be needed in the iomap code, bringing new semantics to other filesystems. Another problem arises when again the buffered and direct ios are mixed, invalidation fails, then -EIO is set on the mapping and fsync will fail, though there's no real error. There have been discussions how to fix that, but revert seems to be the least intrusive option. Link: https://lore.kernel.org/linux-btrfs/20200528192103.xm45qoxqmkw7i5yl@fiona/ Signed-off-by: David Sterba <dsterba@suse.com>
2020-06-13net: ethernet: ti: ale: fix allmulti for nu type aleGrygorii Strashko1-9/+40
On AM65xx MCU CPSW2G NUSS and 66AK2E/L NUSS allmulti setting does not allow unregistered mcast packets to pass. This happens, because ALE VLAN entries on these SoCs do not contain port masks for reg/unreg mcast packets, but instead store indexes of ALE_VLAN_MASK_MUXx_REG registers which intended for store port masks for reg/unreg mcast packets. This path was missed by commit 9d1f6447274f ("net: ethernet: ti: ale: fix seeing unreg mcast packets with promisc and allmulti disabled"). Hence, fix it by taking into account ALE type in cpsw_ale_set_allmulti(). Fixes: 9d1f6447274f ("net: ethernet: ti: ale: fix seeing unreg mcast packets with promisc and allmulti disabled") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-06-13net: ethernet: ti: am65-cpsw-nuss: fix ale parameters initGrygorii Strashko1-1/+1
The ALE parameters structure is created on stack, so it has to be reset before passing to cpsw_ale_create() to avoid garbage values. Fixes: 93a76530316a ("net: ethernet: ti: introduce am65x/j721e gigabit eth subsystem driver") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-06-13net: atm: Remove the error message according to the atomic contextLiao Pingfang1-3/+1
Looking into the context (atomic!) and the error message should be dropped. Signed-off-by: Liao Pingfang <liao.pingfang@zte.com.cn> Signed-off-by: David S. Miller <davem@davemloft.net>