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2015-04-03drm: rockchip: Turn off VT switching on suspendCaesar Wang1-0/+3
drm/rockchip already has support for disabling all displays on suspend and enabling them on resume. Disable automatic VT switching on suspend by the pm console tracking layer. Tested on veyron, used `echo mem > sys/power/state` => verified no VT switch Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2015-04-03drm/rockchip: register all connectors after bindDaniel Kurtz1-0/+19
Register connectors with userspace after all components are bound. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-by: Dominik Behr <dbehr@chromium.org> drm_connector_get_name -> connector->name This patch is necessary to make X11 see screens it seems. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-04-03drm/rockchip: fix clk enable disable mismatch in vop_crtc_mode_setHeiko Stuebner1-8/+10
The function disables the dclk at the beginning, so don't simply return when an error happens, but instead enable the clock again, so that enable and disable calls are balanced. ret_clk is introduced to hold the clk_enable result and not mangle the original error code. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-04-02drm/panel: Add support for Ampire AM-800480R3TMQW-A1H 800x480 7" panelPhilipp Zabel2-0/+35
This adds support for the AM-800480R3TMQW-A1H 7" 800x480 panel to the DRM simple panel driver. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02of: Add vendor prefix for Ampire Co., Ltd.Philipp Zabel1-0/+1
Add Ampire Co., Ltd. to the list of device tree vendor prefixes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: Add display timing for HannStar HSD070PWW1Philipp Zabel1-13/+13
The HannStar HSD070PWW1 LVDS panel data sheet lists allowed ranges additionally to the typical values for pixel clock rate (64.3-82 MHz) and blanking intervals (54-681 clock cycles horizontally, 3-23 lines vertically). This patch replaces this panel's display mode with the display timing information to describe acceptable timings. Since the HSYNC and VSYNC are unused, the distribution between front porches, back porches, and sync pulse lengths was chosen at will. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: simple: Add display timing supportPhilipp Zabel2-0/+43
The simple panel driver's ->get_modes() implementation calculates the display mode list from the typical timings and the ->get_timings() implementation returns the timings to the connected encoder for mode validation and fixup. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> [treding@nvidia.com: select VIDEOMODE_HELPERS] Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: Add display timing supportPhilipp Zabel1-0/+5
Many panel data sheets, additionally to typical values, list allowed ranges for timings such as hsync/vsync lengths, porches, and the pixel clock rate. These can be stored in a struct display_timing, to be used by an encoder mode_fixup callback to clamp user provided timing values or to validate workarounds for clock source limitations. This patch adds a new drm_panel_funcs callback that returns the panel's available display_timing entries. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: Add support for OrtusTech COM43H4M85ULC panelPhilipp Zabel2-0/+34
This adds support for the COM43H4M85ULC 3.7" 800x480 panel to the DRM simple panel driver. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02of: Add vendor prefix for Ortus Technology Co., Ltd.Philipp Zabel1-0/+1
Add Ortus Technology Co., Ltd. to the list of device tree vendor prefixes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: Add bus format for Giantplus GPG482739QS5 panelPhilipp Zabel1-0/+1
This patch adds the bus_format field to the GPG482739QS5 panel structure. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: simple: Add support for AUO b101ean01 panelHuang Lin2-0/+33
The AUO b101ean01 panel is a 10.1" 1280x800 panel which can be supported by the simple panel driver. Signed-off-by: Huang Lin <hl@rock-chips.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: simple: Add support for Innolux ZJ070NA-01PMichael Grzeschik2-0/+33
The Innolux ZJ070NA-01P is a 7.0" TFT LCD panel with an integrated LED backlight unit. This panel is used on the Technexion Toucan. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: simple: Add support for Innolux AT043TN24Nicolas Ferre2-0/+35
The Innolux AT043TN24 4.3" WQVGA TFT LCD panel. This panel with backlight is found in PDA 4.3" LCD screen (TM43xx series for instance). Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: simple: Add support for Shelly SCA07010-BFN-LNNBoris BREZILLON2-0/+33
The Shelly SCA07010-BFN-LNN is a 7.0" WVGA TFT LCD panel. This panel with backlight is found in PDA 7" LCD screen (TM70xx series for instance). Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: simple: Add support for Samsung LTN140AT29 panelStéphane Marchesin2-0/+33
This panel is used by the Nyan Blaze board and can be supported by the simple-panel driver. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> [tomeu.vizoso@collabora.com: add device tree binding document] Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: sor: Reset during initializationTomeu Vizoso1-0/+18
As there isn't a way for the firmware on the Nyan Chromebooks to hand over the display to the kernel, and the kernel isn't redoing the whole configuration at present. With this patch, the SOR is brought to a known state and we get correct display on every boot. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: gem: Return 64-bit offset for mmap(2)Sean Paul1-1/+2
On 64-bit targets, tegra_gem_mmap() only returns a partial offset to userspace. As such, subsequent calls to mmap(2) may fail. Change the arguments to use a 64-bit offset to fix this. Signed-off-by: Sean Paul <seanpaul@chromium.org> Acked-by: Erik Faye-Lund <kusmabite@gmail.com> [treding@nvidia.com: tweak commit message] Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: hdmi: Name register fields consistentlyThierry Reding2-2/+2
Name the fields of the SOR_SEQ_CTL register consistently. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: hdmi: Resets are synchronousThierry Reding1-1/+1
Resets on Tegra are synchronous, so keep the clock enabled while asserting the reset. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: dc: Document tegra_dc_state_setup_clock()Thierry Reding1-0/+12
This function is called by output drivers so should be documented. While at it, move it to a more appropriate location. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: dc: Remove unused callbacksThierry Reding1-2/+0
The ->mode_set() and ->mode_set_base() callbacks are no longer used with full atomic mode-setting drivers, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: dc: Remove unused functionThierry Reding2-22/+0
The tegra_dc_setup_clock() function is unused after the conversion to atomic mode-setting, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: dc: Use base atomic state helpersThierry Reding1-13/+18
Instead of duplicating the code, make use of the newly introduced atomic state duplicate and destroy helpers. This allows changes to the base atomic state handling to automatically propagate to the Tegra driver and thereby prevent breakage resulting from both copies going out of sync. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/atomic: Add helpers for state-subclassing driversThierry Reding2-16/+142
Drivers that subclass CRTC, plane or connector state need to carefully duplicate the code that the atomic helpers have. This is bound to cause breakage eventually because it requires auditing all drivers and update them when code is added to the helpers. In order to avoid that, implement new helpers that perform the required steps when copying and destroying state. These new helpers are exported so that state-subclassing drivers can use them. The default helpers are implemented using them as well, providing a single location that needs to be changed when adding to base atomic states. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: dc: Implement hardware VBLANK counterThierry Reding4-13/+35
The display controller on Tegra can use syncpoints to count VBLANK events. syncpoints are 32-bit unsigned integers, so well suited as VBLANK counters. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02gpu: host1x: Export host1x_syncpt_read()Thierry Reding2-0/+7
This function is used to read the current value of the syncpt and is useful in situations where drivers don't schedule work and wait for the syncpoint to increment. One particular use-case is using the syncpoint as a VBLANK counter. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: sor: Dump registers via debugfsThierry Reding1-6/+165
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: sor: Registers are 32-bitThierry Reding1-7/+6
Use a sized unsigned 32-bit data type (u32) to store register contents. The SOR registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: Provide debugfs file for the IOVA spaceThierry Reding1-0/+10
The Tegra DRM driver uses a single IO virtual address space for buffer mappings. Provide a table of the address space usage in debugfs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: dc: Check for valid parent clockThierry Reding1-0/+3
Check that the desired parent clock is indeed a valid parent for the display controller clock. This is purely cosmetic at this point since the parent clocks are specified in DT and all the currently defined parents are in fact valid parents of the display controller clock. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-01drm/msm/mdp5: Enable DSI connector in msm drm driverHai Li8-7/+497
This change adds the support in mdp5 kms driver for single and dual DSI. Dual DSI case depends on the framework API and sequence change to support dual data path. v1: Initial change v2: Address Rob Clark's comment - Separate command mode encoder to a new file mdp5_cmd_encoder.c - Rebase to not depend on msm_drm_sub_dev change Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm: Initial add DSI connector supportHai Li8-0/+3423
This change adds the DSI connector support in msm drm driver. v1: Initial change v2: - Address comments from Archit + minor clean-ups - Rebase to not depend on msm_drm_sub_dev change [Rob's comment] v3: Fix issues when initialization is failed Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm: Add split display interfaceHai Li1-0/+4
This change is to add an interface to MDP for connector devices setting split display information. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Move *_modeset_init out of construct_encoder functionHai Li1-35/+54
This change is to make the content in construct_encoder reflect its name. Also, DSI connector may be connected to video mode or command mode encoder, so that 2 different encoders need to be constructed for DSI. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm: export tile-group functionsRob Clark1-0/+2
Normally these are called from within drm core, from the EDID parsing code. But for dual-dsi in some drivers (at least drm/msm) we need to call these from the driver. So they should be exported. Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: Dave Airlie <airlied@redhat.com>
2015-04-01drm/msm/mdp5: Remove CTL flush dummy bitsStephane Viau1-11/+0
This TODO can now be removed and replaced by the previous patch "drm/msm/mdp5: Update headers (add CTL flush bits)" Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update headers (add CTL flush bits)Stephane Viau1-2/+10
Some upcoming targets have more bits to set in CTL_FLUSH registers. Example: msm8x16 needs to set TIMING1 bit so that some of the INTF1's interface registers get flushed. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Add hardware configuration for msm8x16Stephane Viau1-1/+51
This change adds the hw configuration for msm8x16 chipsets in mdp5_cfg module. Note that only one external display interface is present in this configuration (DSI) but has not been enabled yet. It will be enabled once drm/msm driver supports DSI connectors. v2: add CTL flush register's hardware mask [pointed by Archit] Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Get SMP client list from mdp5_cfgStephane Viau3-24/+41
SMP blocks are configured for specific client IDs (ports). These client IDs can be different from one chip to another for a given pipe. e.g.: DMA0 pipe fetch Y component is connected to: - port #10 for MDP5 v1.3 - port #4 for MDP5 v1.6 In order to be compatible for upcoming versions of MDP5, the client ID list is passed through the MDP5 config module rather than using a list of hard-coded enum values. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update headers (remove enum mdp5_client_id)Stephane Viau1-34/+7
This patch contains the generated header file of the following change "drm/msm/mdp5: Get SMP client list from mdp5_cfg". Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Separate MDP5 domain from MDSS domainStephane Viau7-38/+48
MDP block is actually contained inside the MDSS block. For some chipsets, the base address of the MDP registers is different from the current (assumed) 0x100 offset. Like CTL and LM blocks, this changes introduce a dynamic offset for the MDP instance, which can be found out at runtime, once the MDSS HW version is read. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update headers (introduce MDP5 domain)Stephane Viau1-85/+118
This change contains the generated header file for the following change "drm/msm/mdp5: Separate MDP5 domain from MDSS domain". Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/dsi: Update generated DSI header fileHai Li1-42/+376
Prepare for initial DSI implementation Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Fix PIPE source image size settingsHai Li1-2/+2
The width and height in SSPP_SRC_IMG_SIZE register should be the size of the entire source framebuffer, not the fetch size. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update generated mdp5 header file with DSI supportHai Li1-0/+105
This change adds the registers in mdp5 ping pong blocks and split display control registers. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Add pingpong entry to mdp5 config tableHai Li2-0/+9
Pingpong register base addresses are different across platforms. This change adds this information to config table and initialize the values for 8x74 and 8084. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Make the intf connection in config moduleStephane Viau3-49/+75
Up until now, we assume that eDP is tight to intf_0 and HDMI to intf_3. This information shall actually come from the mdp5_cfg module since it can change from one chip to another. v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit] v3: add sanity check before writing in INTF_TIMING_ENGINE_EN registers Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Add START signal to kick off certain pipelinesStephane Viau7-97/+276
Some interfaces (WB, DSI Command Mode) need to be kicked off through a START Signal. This signal needs to be sent at the right time and requests in some cases to keep track of the pipeline status (eg: whether pipeline registers are flushed AND output WB buffers are ready, in case of WB interface). Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Enhance operation mode for pipeline configurationStephane Viau7-74/+159
DSI and WB interfaces need a more complex pipeline configuration than the current mdp5_ctl_set_intf(). For example, memory output connections need to be selected for WB. Interface mode (Video vs. Command modes) also need to be configured for DSI. This change takes care of configuring the whole pipeline as far as operation mode goes. DSI and WB interfaces will be added later. v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit] Signed-off-by: Stephane Viau <sviau@codeaurora.org> [Remove temp bisectability hack -Rob] Signed-off-by: Rob Clark <robdclark@gmail.com>
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