Age | Commit message (Collapse) | Author | Files | Lines | |
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2018-03-20 | clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks | 1 | -0/+351 | ||
This adds a new driver for the USB PHY clocks in the CFGCHIP2 syscon register on TI DA8XX-type SoCs. The USB0 (USB 2.0) PHY clock is an interesting case because it calls clk_enable() in a reentrant way. The USB 2.0 PSC only has to be enabled temporarily while we are locking the PLL, which takes place during the clk_enable() callback. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> | |||||
2018-03-20 | clk: davinci: New driver for TI DA8XX CFGCHIP clocks | 3 | -0/+462 | ||
This adds a new driver for the gate and multiplexer clocks in the CFGCHIPn syscon registers on TI DA8XX-type SoCs. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |