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2019-04-17phy: phy-meson-gxl-usb2: get optional clock by devm_clk_get_optional()Chunfeng Yun1-8/+3
Use devm_clk_get_optional() to get optional clock Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: socionext: get optional clock by devm_clk_get_optional()Chunfeng Yun2-14/+6
Use devm_clk_get_optional() to get optional clock Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: qcom-qusb2: get optional clock by devm_clk_get_optional()Chunfeng Yun1-8/+3
Use devm_clk_get_optional() to get optional clock Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: phy-mtk-tphy: get optional clock by devm_clk_get_optional()Chunfeng Yun1-7/+3
Use devm_clk_get_optional() to get optional clock Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: renesas: rcar-gen3-usb2: enable/disable independent irqsYoshihiro Shimoda1-25/+160
Since the previous code enabled/disabled the irqs both OHCI and EHCI, it is possible to cause unexpected interruptions. To avoid this, this patch creates multiple phy instances from phandle and enables/disables independent irqs by the instances. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: renesas: rcar-gen3-usb2: Use pdev's device pointer on dev_vdbg()Yoshihiro Shimoda1-4/+6
To implement multiple phy instances in the future, this patch uses pdev's device pointer on dev_vdbg() instead of the phy's device pointer. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17dt-bindings: phy: rcar-gen3-phy-usb2: Revise #phy-cells propertyYoshihiro Shimoda1-1/+7
To have the detailed property on each PHY specifier, this patch revises the #phy-cells property. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: rcar-gen3-usb2: Add support for r8a77470Biju Das2-7/+34
This patch adds support for r8a77470 (RZ/G1C). We can reuse this driver for initializing timing/interrupt generation registers. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: renesas: phy-rcar-gen2: Add support for r8a77470Biju Das1-12/+118
This patch adds support for RZ/G1C (r8a77470) SoC. RZ/G1C SoC has a PLL register shared between hsusb0 and hsusb1. Compared to other RZ/G1 and R-Car Gen2/3, USB Host needs to deassert the pll reset. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-and-Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17dt-bindings: rcar-gen3-phy-usb2: Add r8a77470 supportBiju Das1-2/+4
Document RZ/G1C (R8A77470) SoC bindings. For RZ/G1C, this driver is used to enable interrupt generation and initializing timing registers which is part of phy_init code. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17dt-bindings: phy: rcar-gen2: Add r8a77470 supportBiju Das1-4/+53
Add USB PHY support for r8a77470 SoC. Renesas RZ/G1C (R8A77470) USB PHY is similar to the R-Car Gen2 family, but has the below feature compared to other RZ/G1 and R-Car Gen2/3 SoCs It has a shared pll reset for usbphy0/usbphy1 and this register reside in usbphy0 block. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ti-pipe3: Fix PCIe power up sequenceRoger Quadros1-6/+6
TRM [1] mentions that we need to power up PCIESS_PHY_TX and PCIESS_PHY_RX before configuring PCIe_PHY_RX SCP settings. See "Table 26-81. PCIePHY Subsystem Low-Level Programming Sequence". [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ti-pipe3: Fix SATA & USB PHY power up sequenceRoger Quadros1-14/+30
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence" in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ti-pipe3: improve DPLL stability for SATA & USBRoger Quadros1-42/+173
For increased DPLL stability use the settings recommended in the TRM [1] for PHY_RX registers for SATA and USB. For SATA we need to use spread spectrum settings even though we don't have spread spectrum enabled. The suggested non-spread spectrum settings don't work. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ti-pipe3: Introduce mode property in driver dataRoger Quadros1-36/+57
Introduce a mode property in the driver data so that we don't have to keep using "of_device_is_compatible()" throughtout the driver. No functional change. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ti-pipe3: fix missing bit-wise or operator when assigning valColin Ian King1-1/+1
There seems to be a missing bit-wise or operator when setting val, fix this by adding it in. Fixes: 2796ceb0c18a ("phy: ti-pipe3: Update pcie phy settings") Cc: stable@vger.kernel.org # v4.19+ Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: mediatek: Add UFS M-PHY driverStanley Chu3-0/+256
Add UFS M-PHY driver on MediaTek chipsets. Signed-off-by: Stanley Chu <stanley.chu@mediatek.com> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>