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2016-04-27ARM: dts: at91: sama5d2: add shutdown controller nodeNicolas Ferre2-0/+18
Add the SAMA5D2-Compatible Shutdown Controller node to sama5d2.dtsi and the use of it in the sama5d2 Xplained board dts file. Enable the RTC wakeup event and the "wake up" button support through the input "0" that is present on the board. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2016-04-27ARM: dts: at91: sama5d4: add watchdog interrupt propertyNicolas Ferre1-0/+1
The "interrupts" property is missing from the watchdog node. Add it with highest priority value of 7. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2016-04-26ARM: dts: STi: STih407: Switch LPC mode from RTC to ClocksourceLee Jones1-1/+1
This aligns with the internal configuration. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2016-04-26ARM: dts: STiH407: Move over to using the 'reserved-memory' API for obtaining DMA memoryLee Jones1-8/+39
Doing so saves quite a bit of code in the driver. For more information on the 'reserved-memory' bindings see: Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt Suggested-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2016-04-26ARM: dts: STiH407: Add nodes for RemoteProcLee Jones1-0/+40
Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2016-04-26ARM: dts: STi: stih407-family: Add nodes for MailboxLee Jones1-0/+33
This patch supplies the Mailbox Controller nodes. In order to request channels, these nodes will be referenced by Mailbox Client nodes. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2016-04-26ARM: dts: STi: STiH407: Provide CPU with a means to look-up Major numberLee Jones1-0/+1
This is used for CPU Frequency Scaling. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2016-04-26ARM: dts: STi: STiH407: Link CPU with its voltage supplyLee Jones1-0/+1
Used for Voltage Scaling using CPUFreq. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2016-04-26ARM: dts: STi: STiH407: Provide CPU with clocking informationLee Jones1-0/+4
Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2016-04-26ARM: dts: STi: STiH407: Provide generic (safe) DVFS configurationLee Jones1-0/+14
You'll notice that the voltage cell is populated with 0's. Voltage information is very platform specific, even depends on 'cut' and 'substrate' versions. Thus it is left blank for a generic (safe) implementation. If other nodes/properties are provided by the bootloader, the ST CPUFreq driver will over-ride these generic values. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2016-04-26ARM: dts: introduce MPS2 AN399/AN400Vladimir Murzin2-1/+95
Application Notes 399 and 400 shares the same memory map and features. Both are shipped with Cortex-M7 and have the same peripheral as AN385/AN386, but with different location of PSRAM and Ethernet controller. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2016-04-26ARM: dts: introduce MPS2 AN385/AN386Vladimir Murzin3-0/+334
Application Notes 385 and 386 shares the same memory map and features except the CPU is used. AN385 is supplied with Cortex-M3 CPU and AN386 is supplied with Cortex-M4. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2016-04-26ARM: dts: at91: fix typo in sama5d2 PIN_PD24 descriptionFlorian Vallee1-2/+2
Fix a typo on PIN_PD24 for UTXD2 and FLEXCOM4_IO3 which were wrongly linked to PIN_PD23). Signed-off-by: Florian Vallee <fvallee@eukrea.fr> Fixes: 7f16cb676c00 ("ARM: at91/dt: add sama5d2 pinmux") Cc: stable@vger.kernel.org # v4.4+ [nicolas.ferre@atmel.com: add commit message, changed subject] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2016-04-26ARM: boot: dts: Add Western Digital My Book World Edition device treeNeil Armstrong2-0/+114
Add Western Digital My Book World Edition device tree based on Oxford Semiconductor OX810SE SoC. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2016-04-26dt-bindings: Add Western Digital to vendor prefixesNeil Armstrong1-0/+1
Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>