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2022-02-28ARM: dts: aspeed: everest: Add RTC battery gpio nameJoel Stanley1-3/+1
This is the documented name used for OpenBMC systems: https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md#rtc-battery-voltage-read-enable Link: https://lore.kernel.org/r/20220222041559.68651-3-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-28ARM: dts: aspeed: rainer: Add RTC battery gpio nameJoel Stanley1-1/+1
This is the documented name used for OpenBMC systems: https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md#rtc-battery-voltage-read-enable Link: https://lore.kernel.org/r/20220222041559.68651-2-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-28ARM: dts: aspeed: Add ASRock ROMED8HM3 BMCZev Weiss2-0/+260
This is a half-width, single-socket Epyc server board with an AST2500 BMC. This device tree is sufficient for basic OpenBMC functionality, but we'll need to add a few more devices (as driver support becomes available) before it's fully usable. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220105101719.7093-1-zev@bewilderbeest.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-28ARM: dts: aspeed: rainier: Remove SPI NOR controllersJoel Stanley1-24/+0
Early Rainier builds had SPI NOR as a fallback boot device when eMMC was not programmed. Most systems don't have the NOR populated, so remove it from the device tree as it is not used. Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220120063307.63898-1-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-28ARM: dts: aspeed: mtjade: Move all adc sensors into iio-hwmon nodeQuan Nguyen1-11/+2
Move adc14 and adc15 (battery sensor) into single iio-hwmon node to correct label to be read by single application for all adc sensors. Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220228000242.1884-6-quan@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-28ARM: dts: aspeed: mtjade: Rename GPIO hog nodes to match schema.Quan Nguyen1-1/+1
GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to the DT schema. Rename the node to pass dtbs_check. Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220228000242.1884-5-quan@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-28ARM: dts: aspeed: mtjade: Update host0-ready pinQuan Nguyen1-1/+1
Update the input GPIO that indicates Host ready. Link: https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md#host-ready Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220228000242.1884-4-quan@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-28ARM: dts: aspeed: mtjade: Update rtc-battery-voltage-read-enable pinQuan Nguyen1-1/+1
Update the output pin name that enables reading RTC battery voltage. Link: https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md#rtc-battery-voltage-read-enable Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220228000242.1884-3-quan@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-28ARM: dts: aspeed: mtjade: Enable secondary flashQuan Nguyen1-0/+7
Enable the secondary flash of the Ampere's Mt. Jade's BMC. Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220228000242.1884-2-quan@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-25ARM: tegra: tamonten: Fix I2C3 pad settingRichard Leitner1-3/+3
This patch fixes the tristate configuration for i2c3 function assigned to the dtf pins on the Tamonten Tegra20 SoM. Signed-off-by: Richard Leitner <richard.leitner@skidata.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-25arm64: tegra: Drop arm,armv8-pmuv3 compatible stringThierry Reding2-3/+3
The arm,armv8-pmuv3 compatible string is meant to be used only for software models and not silicon chips. Drop them and use silicon- specific compatible strings instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-25arm64: dts: renesas: spider: Complete SCIF3 descriptionGeert Uytterhoeven1-0/+23
Complete the description of the serial console by adding RTS/CTS, the external clock crystal, and pin control. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/8e5701ca2a5f5925918217ab79e8489535339e7b.1645458249.git.geert+renesas@glider.be
2022-02-25arm64: dts: renesas: r8a779f0: Add pinctrl device nodeGeert Uytterhoeven1-0/+6
Add a device node for the Pin Function Controller on the Renesas R-Car S4-8 (R8A779F0) SoC. Note that the register block does not include registers for banks 4-7, as they can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/cf4d261ba1253879e117f1598b9f47798cbda635.1645458249.git.geert+renesas@glider.be
2022-02-25ARM: dts: at91: sama7g5: add oppsClaudiu Beznea1-0/+38
Add OPPs for SAMA7G5 along with clock for CPU. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-9-claudiu.beznea@microchip.com
2022-02-25ARM: dts: at91: sama7g5ek: set regulator voltages for standby stateClaudiu Beznea1-0/+5
Set regulator voltages for standby state to avoid wrong behavior of system while in standby. The CPU voltage has been chosen as being the one corresponding to OPP=600MHz. Next commit will set the 600MHz OPP as the suspend OPP. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-8-claudiu.beznea@microchip.com
2022-02-25ARM: dts: at91: fix low limit for CPU regulatorClaudiu Beznea1-1/+1
Fix low limit for CPU regulator. Otherwise setting voltages lower than 1.125V will not be allowed (CPUFreq will not be allowed to set proper voltages on proper frequencies). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-7-claudiu.beznea@microchip.com
2022-02-25ARM: dts: at91: sama7g5: Enable can0 and can1 support in sama7g5-ekHari Prasath1-0/+25
Enable the can0 and can1 controllers in sama7g5-ek board along with its pin mux settings. Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220222113924.25799-3-Hari.PrasathGE@microchip.com
2022-02-25ARM: dts: at91: sama7g5: Add can controllers of sama7g5Hari Prasath1-0/+96
Add support for all the six CAN controllers of sama7g5.The internal SRAM of 128KB is split among the CAN controllers for the message RAM elements leaving a small portion reserved for power management. The SRAM split up is as below. Lower 64K: PM 13K can-0 17K can-1 17K can-2 17K Higher 64K: can-3 17K can-4 17K can-5 17K Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220222113924.25799-2-Hari.PrasathGE@microchip.com
2022-02-25ARM: dts: at91: sama7g5: Add crypto nodesTudor Ambarus1-0/+32
Describe and enable the AES, SHA and TDES crypto IPs. Tested with the extra run-time self tests of the registered crypto algorithms. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220208105646.226623-1-tudor.ambarus@microchip.com
2022-02-25ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15Alexandre Torgue2-4/+11
Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs. STM32MP151 is a single A7. STM32MP153/157 is a dual A7. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Marc Zyngier <maz@kernel.org>
2022-02-25ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp13Alexandre Torgue1-4/+4
Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs. STM32MP13 is a single core A7. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Marc Zyngier <maz@kernel.org>
2022-02-25ARM: dts: stm32: remove timer5 duplicate unit-address on stm32f7 seriesFabrice Gasnier4-7/+36
Remove the following warnings seen when building with W=1. Warning (unique_unit_address): /soc/timer@40000c00: duplicate unit-address (also used in node /soc/timers@40000c00) This approach is based on some discussions[1], to restructure the dtsi and dts files. Timer5 is enabled by default on stm32f7 series, to act as clockevent. In order to get rid of the W=1 warning, and be compliant with dt-schemas (e.g. dtbs_check): - In stm32f746.dtsi: . Keep the more complete timers5 description . Remove the most simple timer5 node that is duplicate - In each board: . adopt "st,stm32-timer" compatible for timers5, also add the interrupt . use /delete-property/ and /delete-node/ so the it matches the clockevent bindings Note: all this is done in one shot (e.g. not split) to keep clockevent functionality. [1] https://lore.kernel.org/linux-arm-kernel/Yaf4jiZIp8+ndaXs@robh.at.kernel.org/ Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: remove some timer duplicate unit-address on stm32f7 seriesFabrice Gasnier1-40/+0
Several unused "timer" are duplicate nodes of "timers" nodes. There are two dt-schemas: - timer/st,stm32-timer.yaml: A timer is needed on STM32F7 series, on all boards, to act as clockevent. - mfd/st,stm32-timers.yaml: Timers can be used for other purpose. By default, timer5 is left enabled to be used as clockevent. Remove all other timer clockevent nodes that are currently unused and duplicated. This removes several messages: Warning (unique_unit_address): /soc/timer@.. duplicate unit-address (also used in node /soc/timers@...) Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: Enable EXTI on stm32mp13Alexandre Torgue1-0/+7
As EXTI/GIC mapping has changed between STM32MP15 and STM32MP13, a new compatible is needed to choose mp13 mapping table in stm32-exti driver. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcor-avenger96Erwan Le Ray1-0/+6
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp15xx-dhcor-avenger96 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Delete also usart2 and uart7 DMA property to keep current behavior. Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart4 behavior on stm32mp15xx-dhcom-somErwan Le Ray1-0/+2
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp15xx-dhcom-som board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcom-picoitxErwan Le Ray1-0/+4
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete usart3 and uart8 nodes DMA property in stm32mp15xx-dhcom-picoitx board device tree to keep current behavior. Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcom-pdk2Erwan Le Ray1-0/+4
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete usart3 and uart8 DMA property in stm32mp15xx-dhcom-pdk2 board device tree to keep current behavior. Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcom-drc02Erwan Le Ray1-0/+4
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete usart3 and uart8 nodes DMA property in stm32mp15xx-dhcom-drc02 board device tree to keep current behavior. Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart4 behavior on stm32mp157c-odysseyErwan Le Ray1-0/+2
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp157c-odyssey board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart4 behavior on stm32mp157c-lxa-mc1Erwan Le Ray1-0/+2
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp157c-lxa-mc1 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart nodes behavior on stm32mp157a-stinger96Erwan Le Ray1-0/+6
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp157a-stinger96 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Delete also usart2 and uart7 DMA property to keep current behavior. Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart nodes behavior on stm32mp1-microdev2.0Erwan Le Ray1-0/+4
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp1-microdev2.0 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Delete also uart8 DMA property to keep current behavior. Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart nodes behavior on stm32mp1-microdev2.0-of7Erwan Le Ray1-0/+4
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp1-microdev2.0-of7 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Delete also uart8 DMA property to keep current behavior. Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart4 behavior on stm32mp157a-iot-boxErwan Le Ray1-0/+2
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp157a-iot-box board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart4 behavior on icore-stm32mp1-edimm2.2Erwan Le Ray1-0/+2
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in icore-stm32mp1-edimm2.2 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart4 behavior on icore-stm32mp1-ctouch2Erwan Le Ray1-0/+2
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in icore-stm32mp1-ctouch2 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart4 and uart7 behavior on stm32mp15xx-dkxErwan Le Ray1-0/+4
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp15xx-dkx board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Delete also uart7 DMA property to keep current behavior. Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: keep uart4 behavior on stm32mp157c-ed1Erwan Le Ray1-0/+2
DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp157c-ed1 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: add DMA configuration to UART nodes on stm32mp151Erwan Le Ray1-0/+21
Add DMA configuration in stm32mp15x uart nodes by selecting dma direct mode and alternate REQ/ACK dma protocol for uart. DMA direct mode allows to bypass DMA FIFO. Each DMA request immediately initiates a transfer from/to the memory. This allows USART to get data transferred, even when the transfer ends before the DMA FIFO completion. Default REQ/ACK DMA protocol consists in maintaining ACK signal up to the removal of REQuest and the transfer completion. In case of alternative REQ/ACK protocol, ACK de-assertion does not wait the removal of the REQuest, but only the transfer completion. Due to a possible DMA stream lock when transferring data to/from STM32 USART/UART, select this alternative protocol in STM32 USART/UART nodes. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: use exti 19 as main interrupt to support RTC wakeup on stm32mp157Alexandre Torgue1-1/+1
Link between GIC and exti line is now done inside EXTI driver. So in order to be wake up source exti irqchip has to be used. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: Add CM4 reserved memory, rproc and IPCC on DHCOR SoMMarek Vasut1-0/+56
Add reserved memory nodes for CortexM4 on the STM32MP1 DHCOR SoM, enable rproc to control the CM4 and IPCC mailbox to interact with it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: add MDMA on STM32MP13x SoC familyAmelie Delaunay1-0/+10
MDMA on STM32MP13x SoCs is the same than on STM32MP15x SoCs: it offers up to 32 channels and supports 48 requests. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-25ARM: dts: stm32: add DMA1, DMA2 and DMAMUX1 on STM32MP13x SoC familyAmelie Delaunay1-0/+44
DMA1 and DMA2 on STM32MP13x SoCs are the same than on STM32MP15x SoCs: they offer up to 8 channels and request lines are routed through DMAMUX1. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-02-24arm64: tegra: Enable Jetson Xavier NX USB device modeWayne Chang1-0/+25
This commit enables USB device mode at J5 micro-B USB port of Jetson Xavier NX. Signed-off-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Enable UART instance on 40-pin headerkartik1-0/+6
On P3737 board, UART-A is available on 40-pin header. Enable UART-A for P3737 and change the compatible string to "nvidia,tegra194-hsuart". This allows supporting HW flow control and is the preferred choice for higher baud rates. Signed-off-by: kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add HDA device tree node for Tegra234Mohan Kumar2-0/+21
Add HDA device tree node for Tegra234 chip and for Jetson AGX Orin platform. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Enable device-tree overlay supportJon Hunter1-0/+11
Add the '-@' DTC option for the Jetson TX1, Jetson Nano, Jetson TX2, Jetson TX2 NX, Jetson AGX Xavier, Jetson Xavier NX and Jetson AGX Orin platforms. This option populates the '__symbols__' node that contains all the necessary symbols for supporting device-tree overlays on these platforms. These Jetson platforms have various expansion headers, including a 40-pin GPIO header, that allow various add-on modules to be connected and this permits users to create device-tree overlays for these modules. Please note that this change does increase the size of the resulting DTB from between 30-50%. For example, with v5.17-rc1 increase in size is as follows: tegra210-p2371-2180.dtb: 79580 -> 105744 bytes tegra210-p3450-0000.dtb: 57465 -> 81357 bytes tegra186-p2771-0000.dtb: 64763 -> 99553 bytes tegra186-p3509-0000+p3636-0001.dtb: 48078 -> 62464 bytes tegra194-p2972-0000.dtb: 75303 -> 111545 bytes tegra194-p3509-0000+p3668-0000.dtb: 74762 -> 111995 bytes tegra194-p3509-0000+p3668-0001.dtb: 74578 -> 111748 bytes tegra234-p3737-0000+p3701-0000.dtb: 11229 -> 12917 bytes Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: APE sound card for Jetson AGX OrinSameer Pujar2-0/+1797
Add audio-graph based sound card support on Jetson AGX Orin platform. The sound card binds following modules: * I/O interfaces such as I2S and DMIC (to be specific I2S1, I2S2, I2S4, I2S6 and DMIC3 instances). * HW accelerators such as MVC, SFC, AMX, ADX and Mixer (all the available instances). Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add audio devices on Tegra234Sameer Pujar1-0/+419
Add following devices which are part of APE subsystem * ACONNECT, AGIC and ADMA * AHUB and children (ADMAIF, I2S, DMIC, DSPK, MVC, SFC, AMX, ADX and Mixer) Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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