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2018-12-12ARM: at91: add support in soc driver for LPDDR2 SiPNicolas Ferre2-0/+12
Add some more SiP components to be detected by this soc.c driver. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-12-10soc: amlogic: meson-clk-measure: Add missing REGMAP_MMIO dependencyCorentin Labbe1-0/+1
This patchs adds a missing dependency on REGMAP_MMIO. This cause the following build failure on SPARC: drivers/soc/amlogic/meson-clk-measure.o: In function `meson_msr_probe': meson-clk-measure.c:(.text+0xc4): undefined reference to `__devm_regmap_init_mmio_clk' Signed-off-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-10soc: imx: gpc: Increase GPC_CLK_MAX to 7Leonard Crestez1-1/+1
The DISPLAY power domain on imx6sx has 7 clocks. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-06soc: renesas: rcar-sysc: Fix power domain control after system resumeGeert Uytterhoeven1-19/+9
To control power to a power domain, the System Controller (SYSC) needs the corresponding interrupt source to be enabled, but masked, to prevent the CPU from receiving it. Currently this is handled in the driver's probe() routine, and set up for every domain present, even if it will not be controlled directly by SYSC (CPU domains are powered through the APMU on R-Car Gen2 and later). On R-Car Gen3, PSCI powers down the SoC during system suspend, thus losing any configured interrupt state. Hence after system resume, power domains not controlled through the APMU (e.g. A3IR, A3VC, A3VP) fail to power up. Fix this by replacing the global interrupt setup in the probe() routine by a domain-specific interrupt setup in rcar_sysc_power(), where the domain's power is actually controlled. This brings the code more in line with the flowchart in the Hardware User's Manual. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-06soc: renesas: rcar-sysc: Merge PM Domain registration and linkingGeert Uytterhoeven1-13/+5
Commit 977d5ba4507dfe5b ("soc: renesas: rcar-sysc: Make PM domain initialization more robust") split PM Domain registration and the linking of children to their parents, to accommodate PM Domain tables that list child domains before their parents. However, this failed to realize that parent power domains must be powered up before their children anyway, and that this thus must be reflected by the order in the PM Domain tables. Revert the split, as it did not help anyway. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-06soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpersGeert Uytterhoeven1-15/+4
Until commit 7e8a50df26f4e700 ("soc: renesas: rcar-sysc: Drop legacy handling"), the rcar_sysc_power_{down,up}() helpers were public, as they were called by the legacy (pre-DT) CPU power management code on R-Car H1 and R-Car Gen2 before. As they are just one-line wrappers around rcar_sysc_power(), it makes sense to just remove them. This also avoids a bool/helper/bool conversion in rcar_sysc_power_cpu(), where a bool is checked to call one of two helper functions, which just call rcar_sysc_power() with hardcoded boolean values again. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-06soc: renesas: r8a77990-sysc: Fix initialization order of 3DG-{A,B}Geert Uytterhoeven1-19/+4
The workaround for the wrong hierarchy of the 3DG-{A,B} power domains on R-Car E3 ES1.0 corrected the parent domains. However, the 3DG-{A,B} power domains were still initialized and powered in the wrong order, causing 3DG operation to fail. Fix this by changing the order in the table at runtime, when running on an affected SoC. Fixes: 086b399965a7ee7e ("soc: renesas: r8a77990-sysc: Add workaround for 3DG-{A,B}") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-05dt-bindings: sram: sunxi: Add compatible for the A64 SRAM C1Paul Kocialkowski1-0/+1
This introduces a new compatible for the A64 SRAM C1 section, that is compatible with the SRAM C1 section as found on the A10. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-05dt-bindings: sram: sunxi: Add bindings for the H5 with SRAM C1Paul Kocialkowski1-0/+4
This introduces new bindings for the H5 SoC in the SRAM controller. Because the SRAM layout is different from other SoCs, no backward compatibility is assumed with any of them. However, the C1 SRAM section alone looks similar to previous SoCs, so it is compatible with the initial A10 binding. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-05dt-bindings: sram: Add Allwinner suniv F1C100sMesih Kilinc1-0/+4
The suniv ARMv5 F1C100s chip has similar sram controller to sun4i A10. Add compatible string for it. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-05soc: sunxi: sram: Add support for the H5 SoC system controlPaul Kocialkowski1-0/+4
This adds the H5 SoC compatible to the list of device-tree matches for the SRAM driver. Since the variant is the same as the A64 (that precedes the H5), the same variant description is used. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-05soc: sunxi: sram: Enable EMAC clock access for H3 variantPaul Kocialkowski1-1/+5
Just like the A64 and H5, the H3 SoC uses the system control block to enable the EMAC clock. Add a variant structure definition for the H3 and use it over the A10 one. This will allow using the H3-specific binding for the syscon node attached to the EMAC instead of the generic syscon binding. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-05soc: imx: gpcv2: add support for i.MX8MQ SoCLucas Stach5-7/+237
The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the GPCv2 on the i.MX7, but only controls more power domains with a different mapping. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-05soc: imx: gpcv2: move register access table to domain dataLucas Stach1-20/+24
The valid register ranges are defined by the implemented power domains, which are different between the individual SoCs where the GPCv2 is used. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-05soc: imx: gpcv2: prefix i.MX7 specific definesLucas Stach1-28/+28
So we can add i.MX8M support without introducing name clashes. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-03dmaengine: pxa: make the filter function internalRobert Jarzmik2-14/+2
As the pxa architecture and all its related drivers do not rely anymore on the filter function, thanks to the slave map conversion, make pxad_filter_fn() static, and remove it from the global namespace. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Vinod Koul <vkoul@kernel.org>
2018-12-02soc: mediatek: Add Mediatek CMDQ helperHoulong Wei4-0/+446
Add Mediatek CMDQ helper to create CMDQ packet and assemble GCE op code. Signed-off-by: Houlong Wei <houlong.wei@mediatek.com> Signed-off-by: HS Liao <hs.liao@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-11-30soc: renesas: r8a77980-sysc: Correct A3VIP[012] power domain hierarchyGeert Uytterhoeven2-4/+4
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) renamed the A3VIP power domain on R-Car V3H to A3VIP0, and clarified the power domain hierarchy for the A3VIP[012] power domains. As the definition for the A3VIP0 domain is not yet used from DT, it can just be renamed. Fixes: 7755b40d07a8dba7 ("dt-bindings: power: add R8A77980 SYSC power domain definitions") Fixes: 41d6d8bd8ae94ca9 ("soc: renesas: rcar-sysc: add R8A77980 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-30soc: renesas: r8a77980-sysc: Correct names of A2DP[01] power domainsGeert Uytterhoeven2-4/+4
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) renamed the A2PD0 and A2DP0 power domains on R-Car V3H to A2DP0 resp. A2DP1. As these definitions are not yet used from DT, they can just be renamed. Fixes: 7755b40d07a8dba7 ("dt-bindings: power: add R8A77980 SYSC power domain definitions") Fixes: 41d6d8bd8ae94ca9 ("soc: renesas: rcar-sysc: add R8A77980 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-30soc: renesas: r8a77970-sysc: Correct names of A2DP/A2CN power domainsGeert Uytterhoeven2-5/+5
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) renamed the A2IR2 and A2IR3 power domains on R-Car V3M to A2DP resp. A2CN. As these definitions are not yet used from DT, they can just be renamed. While at it, fix the indentation of the A3IR definition. Fixes: 833bdb47c826a1a6 ("dt-bindings: power: add R8A77970 SYSC power domain definitions") Fixes: bab9b2a74fe9da96 ("soc: renesas: rcar-sysc: add R8A77970 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-30soc: renesas: r8a77970-sysc: Remove non-existent CR7 power domainGeert Uytterhoeven2-2/+0
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) removed the CR7 power domain on R-Car V3M, as this SoC does not have an ARM Cortex-R7 Realtime Core. As this definition was never used from DT, it can just be removed. Fixes: 833bdb47c826a1a6 ("dt-bindings: power: add R8A77970 SYSC power domain definitions") Fixes: bab9b2a74fe9da96 ("soc: renesas: rcar-sysc: add R8A77970 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-30soc: renesas: r8a77965-sysc: Remove non-existent A3IR power domainGeert Uytterhoeven1-1/+0
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) removed the A3IR power domain on R-Car M3-N, as this SoC does not have an Image Processing Unit (IMP-X5). The definition in the DT bindings header cannot be removed yet, until its (incorrect) user has been removed. Fixes: a527709b78b3c997 ("soc: renesas: rcar-sysc: Add R-Car M3-N support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-29drm: msm: Check cmd_db_read_aux_data() for failureStephen Boyd1-0/+5
We need to check the call to cmd_db_read_aux_data() for the error case, so that we don't continue and use potentially uninitialized values for 'pri_count' and 'sec_count'. Otherwise, we get the following compiler warnings: drivers/gpu/drm/msm/adreno/a6xx_gmu.c: In function 'a6xx_gmu_rpmh_arc_votes_init.isra.12': drivers/gpu/drm/msm/adreno/a6xx_gmu.c:943:12: warning: 'pri_count' is used uninitialized in this function [-Wuninitialized] pri_count >>= 1; ^~~ drivers/gpu/drm/msm/adreno/a6xx_gmu.c:948:12: warning: 'sec_count' may be used uninitialized in this function [-Wmaybe-uninitialized] sec_count >>= 1; ^~~ Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reported-by: kbuild test robot <lkp@intel.com> Cc: Jordan Crouse <jcrouse@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Evan Green <evgreen@chromium.org> Cc: Jordan Crouse <jcrouse@codeaurora.org> Cc: Rob Clark <robdclark@gmail.com> Fixes: ed3cafa79ea7 ("soc: qcom: cmd-db: Stop memcpy()ing in cmd_db_read_aux_data()") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Acked-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-29soc: qcom: smd-rpm: Add QCS404 compatibleBjorn Andersson2-0/+2
This patch adds a compatible for the rpm on the Qualcomm QCS404 platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-28soc: amlogic: Add Meson Clock Measure driverNeil Armstrong3-0/+359
The Amlogic Meson SoCs embeds a clock measurer IP to measure the internal clock paths frequencies. The precision is determined by stepping into the duration until the counter overflows. The debugfs slows a pretty summary and each clock can be measured individually aswell. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>