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2020-09-17drm/i915: Configure DP 1.3+ protocol converted HDMI modeVille Syrjälä3-0/+25
2020-09-17drm/i915: Deal with TMDS DFP clock limitsVille Syrjälä2-3/+34
2020-09-17drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock()Ville Syrjälä2-0/+122
2020-09-17drm/i915: Reworkd DP DFP clock handlingVille Syrjälä2-28/+28
2020-09-17drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock()Ville Syrjälä4-36/+22
2020-09-17drm/dp: Pimp drm_dp_downstream_max_bpc()Ville Syrjälä4-28/+46
2020-09-17drm/dp: Add helpers to identify downstream facing port typesVille Syrjälä2-0/+65
2020-09-17drm/i915: Reworkd DFP max bpc handlingVille Syrjälä2-6/+21
2020-09-17drm/dp: Define more downstream facing port capsVille Syrjälä1-1/+7
2020-09-17drm/dp: Define protocol converter DPCD registersVille Syrjälä1-0/+10
2020-09-17drm/i915/lspcon: Do not send infoframes to non-HDMI sinksVille Syrjälä3-7/+11
2020-09-17drm/dp: Dump downstream facing port capsVille Syrjälä1-1/+6
2020-09-16drm/i915/selftests: Push the fake iommu device from the stack to dataChris Wilson1-7/+5
2020-09-16drm/i915: Initialise outparam for error return from wait_for_registerChris Wilson1-1/+2
2020-09-15drm/i915/pll: Centralize PLL_ENABLE register lookupAnusha Srivatsa1-17/+18
2020-09-15drm/i915: Nuke pointless variableVille Syrjälä1-2/+1
2020-09-15drm/i915: Introduce intel_hpd_hotplug_irqs()Ville Syrjälä1-27/+23
2020-09-15drm/i915: Introduce HPD_PORT_TC<n>Ville Syrjälä4-126/+102
2020-09-15drm/i915: Move hpd_pin setup to encoder initVille Syrjälä3-2/+3
2020-09-15drm/i915: Split icp_hpd_detection_setup() into ddi vs. tc partsVille Syrjälä1-21/+27
2020-09-15drm/i915: Configure GEN11_{TBT,TC}_HOTPLUG_CTL for ports TC5/6Ville Syrjälä1-2/+6
2020-09-15drm/i915: Nuke the redundant TC/TBT HPD bit definesVille Syrjälä2-34/+22
2020-09-15drm/i915: Add VBT AUX CH H and IVille Syrjälä2-0/+8
2020-09-15drm/i915: Add VBT DVO ports H and IVille Syrjälä2-2/+8
2020-09-15drm/i915: Add AUX_CH_{H,I} power domain handlingVille Syrjälä1-0/+8
2020-09-15drm/i915: Add PORT_{H,I} to intel_port_to_power_domain()Ville Syrjälä1-0/+4
2020-09-15drm/i915: Add more AUX CHs to the enumVille Syrjälä1-0/+2
2020-09-15drm/i915: Reduce INTEL_DISPLAY_ENABLED to just treat outputs as disconnectedVille Syrjälä13-9/+44
2020-09-15drm/i915: Reduce INTEL_DISPLAY_ENABLED to just removing the outputsVille Syrjälä5-10/+9
2020-09-14drm/i915: Update DRIVER_DATE to 20200914Rodrigo Vivi1-1/+1
2020-09-14drm/i915: Update DRIVER_DATE to 20200914Rodrigo Vivi1-2/+2
2020-09-14drm/i915: Use fb->format->is_yuv for the g4x+ sprite RGB vs. YUV checkVille Syrjälä1-2/+2
2020-09-14drm/i915: Fix g4x+ sprite dotclock limit for upscalingVille Syrjälä1-2/+1
2020-09-14drm/i915: Nuke CACHE_MODE_0 save/restoreVille Syrjälä2-10/+0
2020-09-14drm/i915: Nuke MI_ARB_STATE save/restoreVille Syrjälä2-7/+0
2020-09-14drm/i915: Nuke the magic FBC_CONTROL save/restoreVille Syrjälä2-9/+0
2020-09-14drm/i915: Kill unused savePCH_PORT_HOTPLUGVille Syrjälä1-1/+0
2020-09-11drm/i915: Nuke dpio_phy_iosf_port[]Ville Syrjälä5-23/+14
2020-09-11drm/i915: move gmbus restore to i915_restore_displayJani Nikula1-2/+2
2020-09-11drm/i915: move gen4 GCDGMBUS save/restore to display save/restoreJani Nikula1-9/+12
2020-09-11drm/i915: disable all display features when no displayJani Nikula1-0/+8
2020-09-10drm/i915: Fix slightly botched merge in __reloc_entry_gpuMaarten Lankhorst1-2/+2
2020-09-10drm/i915/gvt: Init vreg GUC_STATUS to GS_MIA_IN_RESETColin Xu1-0/+3
2020-09-10drm/i915/gvt: Add F_CMD_ACCESS for some GEN9 SKU WA MMIO accessColin Xu1-2/+2
2020-09-10drm/i915/gvt: remove F_CMD_ACCESS flag for some registersYan Zhao1-12/+16
2020-09-10drm/i915/gvt: add/modify interfaces for flag F_CMD_ACCESSYan Zhao2-3/+18
2020-09-10drm/i915/gvt: remove flag F_CMD_ACCESSEDYan Zhao2-16/+0
2020-09-10drm/i915/gvt: rename F_IN_CTX flag to F_SR_IN_CTXYan Zhao3-11/+16
2020-09-08Revert "drm/i915/gem: Delete unused code"Dave Airlie1-0/+19
2020-09-08Revert "drm/i915/gem: Async GPU relocations only"Dave Airlie2-27/+289
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