aboutsummaryrefslogtreecommitdiffstats
path: root/tools/perf/scripts/python/export-to-sqlite.py (unfollow)
AgeCommit message (Collapse)AuthorFilesLines
2022-02-09arm64: dts: stratix10: align pl330 node name with dtschemaKrzysztof Kozlowski1-1/+1
Fixes dtbs_check warnings like: pdma@ffda0000: $nodename:0: 'pdma@ffda0000' does not match '^dma-controller(@.*)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-02-09arm64: dts: intel: socfpga_agilex_socdk: align LED node names with dtschemaKrzysztof Kozlowski1-3/+3
Align the LED node names with dtschema to silence dtbs_check warnings like: leds: 'hps0', 'hps1', 'hps2' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-02-09arm64: dts: agilex: align mmc node names with dtschemaKrzysztof Kozlowski1-1/+1
The Synopsys DW MSHC bindings require node name to be 'mmc': dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-02-09arm64: dts: agilex: add board compatible for N5X DKKrzysztof Kozlowski1-0/+1
The Intel SoCFPGA N5X SoC Development Kit is a board with Agilex, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-02-09arm64: dts: agilex: add board compatible for SoCFPGA DKKrzysztof Kozlowski2-0/+2
The Intel SoCFPGA Agilex 10 SoC Development Kit is a board with Agilex, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-02-09arm64: dts: stratix10: align regulator node names with dtschemaKrzysztof Kozlowski2-2/+2
The devicetree specification requires that node name should be generic. The dtschema complains if name does not match pattern, so make the 0.33 V regulator node name more generic. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-02-09arm64: dts: stratix10: align mmc node names with dtschemaKrzysztof Kozlowski1-1/+1
The Synopsys DW MSHC bindings require node name to be 'mmc': dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-02-09arm64: dts: stratix10: move ARM timer out of SoC nodeKrzysztof Kozlowski1-9/+10
The ARM timer is usually considered not part of SoC node, just like other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning: arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dt.yaml: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 13, 3848], [1, 14, 3848], [1, 11, 3848], [1, 10, 3848]]} should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-02-09arm64: dts: stratix10: add board compatible for SoCFPGA DKKrzysztof Kozlowski2-0/+2
The Altera SoCFPGA Stratix 10 SoC Development Kit is a board with Stratix 10, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-02-09ARM: dts: arria10: add board compatible for SoCFPGA DKKrzysztof Kozlowski1-1/+1
The Altera SoCFPGA Arria 10 SoC Development Kit is a board with Arria 10, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-02-09ARM: dts: arria10: add board compatible for Mercury AA1Krzysztof Kozlowski1-1/+1
The Enclustra Mercury AA1 is a module with Arria 10, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-02-09ARM: dts: arria5: add board compatible for SoCFPGA DKKrzysztof Kozlowski1-1/+1
The Altera SoCFPGA Arria V SoC Development Kit is a board with Arria 5, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-02-09dt-bindings: clock: intel,stratix10: convert to dtschemaKrzysztof Kozlowski2-20/+35
Convert the Intel Stratix 10 clock controller bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>