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2021-11-30arm64: dts: qcom: sc7280: Define EC and H1 nodes for IDP/CRDKshitiz Godara3-0/+107
The IDP2 and CRD boards share the EC and H1 parts, so define all related device nodes into a common file and include them in the idp2 and crd dts files to avoid duplication. Signed-off-by: Kshitiz Godara <kgodara@codeaurora.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1638185497-26477-4-git-send-email-quic_rjendra@quicinc.com
2021-11-30arm64: dts: qcom: sc7280-crd: Add device tree files for CRDRajendra Nayak2-0/+32
CRD (Compute Reference Design) is a sc7280 based board, largely derived from the existing IDP board design with some key deltas 1. has EC and H1 over SPI similar to IDP2 2. touchscreen and trackpad support 3. eDP display We just add the barebones dts file here, subsequent patches will add support for EC/H1 and other components. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Tested-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1638185497-26477-3-git-send-email-quic_rjendra@quicinc.com
2021-11-30dt-bindings: arm: qcom: Document qcom,sc7280-crd boardRajendra Nayak1-0/+2
Document the qcom,sc7280-crd board based off sc7280 SoC, The board is also known as hoglin in the Chrome OS builds, so document the google,hoglin compatible as well. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1638185497-26477-2-git-send-email-quic_rjendra@quicinc.com
2021-11-30arm64: dts: qcom: Drop input-name propertyDang Huynh7-10/+0
This property doesn't seem to exist in the documentation nor in source code, but for some reason it is defined in a bunch of device trees. Signed-off-by: Dang Huynh <danct12@riseup.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211123162436.1507341-1-danct12@riseup.net
2021-11-30arm64: dts: qcom: sdm660-xiaomi-lavender: Add volume up buttonDang Huynh1-0/+13
This enables the volume up key. Signed-off-by: Dang Huynh <danct12@riseup.net> Tested-by: Alexey Minnekhanov <alexeymin@postmarketos.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211121170449.1124048-1-danct12@riseup.net
2021-11-30arm64: dts: qcom: msm8916: Add RPM sleep statsStephan Gerhold1-0/+5
MSM8916 is similar to the other SoCs that had the RPM stats node added in commit 290bc6846547 ("arm64: dts: qcom: Enable RPM Sleep stats"). However, the dynamic offset readable at 0x14 seems only available on some of the newer firmware versions. To be absolutely sure, make use of the new qcom,msm8916-rpm-stats compatible that reads the sleep stats from a fixed offset of 0xdba0. Statistics are available for a "vmin" and "xosd" low power mode: $ cat /sys/kernel/debug/qcom_stats/vmin Count: 0 Last Entered At: 0 Last Exited At: 0 Accumulated Duration: 0 Client Votes: 0x0 $ cat /sys/kernel/debug/qcom_stats/xosd Count: 0 Last Entered At: 0 Last Exited At: 0 Accumulated Duration: 0 Client Votes: 0x0 Cc: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211119213953.31970-4-stephan@gerhold.net
2021-11-30arm64: dts: qcom: sm8250: Add CPU opp tablesThara Gopinath1-0/+314
Add OPP tables to scale DDR and L3 with CPUs for SM8250 SoCs. Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211110215330.74257-1-thara.gopinath@linaro.org
2021-11-20arm64: dts: qcom: sdm660-xiaomi-lavender: Add USBAlexey Min1-0/+25
Enable and configure DWC3 and QUSB2 PHY to enable USB functionality on the Redmi Note 7. Signed-off-by: Alexey Min <alexey.min@gmail.com> Co-developed-by: Dang Huynh <danct12@riseup.net> Signed-off-by: Dang Huynh <danct12@riseup.net> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211120214227.779742-9-danct12@riseup.net
2021-11-20arm64: dts: qcom: sdm660-xiaomi-lavender: Enable Simple FramebufferDang Huynh1-0/+18
This lets the user sees the framebuffer console. Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dang Huynh <danct12@riseup.net> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211120214227.779742-8-danct12@riseup.net
2021-11-20arm64: dts: qcom: sdm660-xiaomi-lavender: Add eMMC and SDDang Huynh1-0/+19
This commit enable the SD card slot and internal MMC. Signed-off-by: Dang Huynh <danct12@riseup.net> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211120214227.779742-7-danct12@riseup.net
2021-11-20arm64: dts: qcom: sdm660-xiaomi-lavender: Add PWRKEY and RESINDang Huynh1-0/+10
This enables the volume down key as well as the power button. Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dang Huynh <danct12@riseup.net> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211120214227.779742-5-danct12@riseup.net
2021-11-20arm64: dts: qcom: sdm660-xiaomi-lavender: Add RPM and fixed regulatorsDang Huynh1-0/+266
Add most of the RPM PM660/PM660L regulators and the fixed ones, defining the common electrical part of this platform. Signed-off-by: Dang Huynh <danct12@riseup.net> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211120214227.779742-4-danct12@riseup.net
2021-11-20arm64: dts: qcom: sdm630-pm660: Move RESIN to pm660 dtsiDang Huynh2-9/+19
It's not worth duplicating the same node over and over again, so let's keep the common bits in the pm660 DTSI, making only changing the status and keycode necessary. Also, disable RESIN/PWR by default just in case if there are devices that doesn't use them. Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dang Huynh <danct12@riseup.net> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211120214227.779742-3-danct12@riseup.net
2021-11-20arm64: dts: qcom: sdm630: Assign numbers to eMMC and SDDang Huynh1-0/+5
This makes eMMC/SD device number consistent. Reviewed-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Dang Huynh <danct12@riseup.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211120214227.779742-2-danct12@riseup.net
2021-11-20arm64: dts: qcom: sc7280: Fix 'interrupt-map' parent address cellsPrasad Malisetty1-4/+4
Update interrupt-map parent address cells for sc7280 Similar to existing Qcom SoCs. Fixes: 92e0ee9f8 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1637060508-30375-4-git-send-email-pmaliset@codeaurora.org
2021-11-20arm64: dts: qcom: sc7280: Add pcie clock supportPrasad Malisetty1-1/+2
Add pcie clock phandle for sc7280 SoC. Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1637060508-30375-3-git-send-email-pmaliset@codeaurora.org
2021-11-20arm64: dts: qcom: sc7280: Fix incorrect clock namePrasad Malisetty1-1/+1
Replace pcie_1_pipe-clk clock name with pcie_1_pipe_clk To match with dt binding. Fixes: ab7772de8612 ("arm64: dts: qcom: SC7280: Add rpmhcc clock controller node") Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1637060508-30375-2-git-send-email-pmaliset@codeaurora.org
2021-11-20arm64: dts: qcom: sc7180: Fix ps8640 power sequence for Homestar rev4yangcong1-0/+4
When powering up the ps8640, we need to deassert PD right after we turn on the vdd33 regulator. Unfortunately, the vdd33 regulator takes some time (~4ms) to turn on. Add in the delay for the vdd33 regulator so that when the driver deasserts PD that the regulator has had time to ramp. Signed-off-by: yangcong <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211115030155.9395-1-yangcong5@huaqin.corp-partner.google.com
2021-11-20arm64: dts: qcom: sm8350: Add LLCC nodeKonrad Dybcio1-0/+6
Configure the Last-Level Cache Controller for SM8350. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-16-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: sm8350-sagami: Configure remote processorsKonrad Dybcio1-0/+26
Configure ADSP, CDSP, MPSS, SLPI and IPA on SoMC Sagami. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-15-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: sm8350-sagami: Enable and populate I2C/SPI nodesKonrad Dybcio1-0/+101
Based on current driver availability, add either nodes or comments regarding peripherals connected via I2C/SPI. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-14-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: Add support for Xperia 1 III / 5 IIIKonrad Dybcio4-0/+166
Add support for SONY Xperia 1 III (PDX215) and 5 III (PDX214) smartphones. Both are based on the SM8350 Sagami platform and feature some really high-end specs, such as: - 4K (1 III / PRO-I) / 1080p (5 III), 120Hz HDR OLED 10-bit panels - USB-C 3.1 with HDMI in (yes, phone as display!) and DP out - 5G - 8 or 12 gigs of ram, 128/256/512 gigs of storage - A 3.5mm headphone jack, a RGB notification LED and a uSD card slot :) - IP65/68 dust/water resistance - Dual front-firing speakers and a lot of microphones - Crazy complex camera hardware (especially on the PRO-I), which includes 4 cameras, an RGBIR sensor and a 3D iToF The aforementioned PRO-I (PDX217) is not supported in this patch, because even though it shares most of the code with 1 III, nobody really has it (yet?) This only adds basic support for booting to a USB shell with a bootloader-enabled display, support for all the awesome hardware listed above will (hopefully) come (hopefully) soon. In order to get a working boot image, you need to run (e.g. for 1 III): cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm8350-sony-xperia-\ sagami-pdx215.dtb > .Image.gz-dtb mkbootimg \ --kernel .Image.gz-dtb \ --ramdisk some_initrd.img \ --pagesize 4096 \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --tags_offset 0x100 \ --cmdline "SOME_CMDLINE" \ --dtb_offset 0x1f00000 \ --header_version 1 \ --os_version 11 \ --os_patch_level 2021-10 \ # or newer -o boot.img-sony-xperia-pdx215 Then, you need to flash it on the device and get rid of all the vendor_boot/dtbo mess: fastboot flash boot boot.img-sony-xperia-pdx215 fastboot erase vendor_boot fastboot flash dtbo emptydtbo.img fastboot reboot Where emptydtbo.img is a tiny file that consists of 2 bytes (all zeroes), doing a "fastboot erase" won't cut it, the bootloader will go crazy and things will fall apart when it tries to overlay random bytes from an empty partition onto a perfectly good appended DTB. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-13-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: sm8350: Assign iommus property to QUP WRAPsKonrad Dybcio1-0/+3
Assign the iommus property to allow access to QUP hosts that were not set up by the bootloader. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-12-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: sm8350: Set up WRAP2 QUPsKonrad Dybcio1-0/+200
Set up I2C&SPI hosts and UARTs connected to WRAP2 and their respective pins. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-11-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: sm8350: Set up WRAP1 QUPsKonrad Dybcio1-11/+202
Set up I2C&SPI hosts and UARTs connected to WRAP1 and their respective pins. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-10-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: sm8350: Set up WRAP0 QUPsKonrad Dybcio1-0/+287
Set up I2C&SPI hosts and UARTs connected to WRAP0 and their respective pins. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-9-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: sm8350: Describe GCC dependency clocksKonrad Dybcio1-2/+24
Add all the clock names that the GCC driver expects to get via DT, so that the clock handles can be filled as the development progresses. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-8-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: *8350* Consolidate PON/RESIN usageKonrad Dybcio2-3/+13
Disable PON/RESIN keys by default and keep the RESIN keycode set-per-board, as these settings are not common between devices (one cannot even assume all devices have buttons nowadays..). Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-7-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: sm8350: Shorten camera-thermal-bottom nameKonrad Dybcio1-1/+1
Thermal zone names should not be longer than 20 names, which is indicated by a message at boot. Change "camera-thermal-bottom" to "cam-thermal-bottom" to fix it. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-6-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: sm[68]350: Use interrupts-extended with pdc interruptsKonrad Dybcio2-4/+4
Using interrupts = <&pdc X Y> makes the interrupt framework interpret this as the &pdc-nth range of the main interrupt controller (GIC). Fix it. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-5-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: sm8350: Specify clock-frequency for arch timerKonrad Dybcio1-0/+1
Arch timer runs at 19.2 MHz. Specify the rate in the timer node. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-4-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: sm8350: Add redistributor stride to GICv3Konrad Dybcio1-0/+2
The redistributor properties were missing. Add them. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-3-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: sm8350: Add missing QUPv3 ID2Konrad Dybcio1-0/+12
Add the missing third QUPv3 master node. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-2-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSIKonrad Dybcio3-2/+1
Almost any board that boots and has a way to interact with it (say for the rare cases of just-pstore or let's-rely-on-bootloader-setup) needs to set some GPIOs, so it makes no sense to include gpio.h separately each time. Hence move it to SoC DTSI. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-1-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: Add missing vdd-supply for QUSB2 PHYShawn Guo4-0/+5
QUSB2 PHY requires vdd-supply for digital circuit operation. Add it for platforms that miss it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210928022002.26286-4-shawn.guo@linaro.org
2021-11-20arm64: dts: qcom: msm8996-xiaomi-common: Change TUSB320 to TUSB320LYassine Oudjana1-2/+2
This platform actually doesn't have TUSB320, but rather TUSB320L. The TUSB320 compatible string was used due to lack of support for TUSB320L, and it was close enough to detect cable plug-in and direction, but it was limited to upstream facing port mode only. Now that support for TUSB320L is added[1], change node name and compatible to match and allow it to be properly reset and have its mode set to dual-role port. [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=ce0320bd3872038569be360870e2d5251b975692 Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211104111454.105875-1-y.oudjana@protonmail.com
2021-11-20arm64: dts: qcom: msm8996-xiaomi-scorpio: Add touchkey controllerYassine Oudjana1-0/+28
Add a node and pin states for Cypress StreetFighter touchkey controller. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211104104932.104046-1-y.oudjana@protonmail.com
2021-11-20arm64: dts: qcom: msm8996-sony-xperia-tone: fix SPMI regulators declarationDmitry Baryshkov1-13/+16
Device tree for the Sony Xperia tone family of devices specifies S9+S10+S11 SAW regulator as a part of the pmi8994_spmi_regulators device tree node. However PMI8994 does not have these regulators, they are part of the PM8994 device. All other MSM8996-based devices list them in the pm8994_spmi_regulators device tree node. Move them accordingly. Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211104002949.2204727-5-dmitry.baryshkov@linaro.org
2021-11-20arm64: dts: qcom: msm8994-sony-xperia-kitakami: correct lvs1 and lvs2 supply propertyDmitry Baryshkov1-1/+1
The qcom_rpm_smd_regulator driver uses vdd_lvs1_2-supply property to specify the supply regulator for LVS1 and LVS2 (following the pin name in the PMIC datasheet). Correct the board's device tree property, so that the regulator supply is setup properly. Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211104002949.2204727-4-dmitry.baryshkov@linaro.org
2021-11-20arm64: dts: qcom: apq8096-db820c: correct lvs1 and lvs2 supply propertyDmitry Baryshkov1-1/+1
The qcom_rpm_smd_regulator driver uses vdd_lvs1_2-supply property to specify the supply regulator for LVS1 and LVS2 (following the pin name in the PMIC datasheet). Correct the board's device tree property, so that the regulator supply is setup properly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211104002949.2204727-3-dmitry.baryshkov@linaro.org
2021-11-20arm64: dts: qcom: apq8096-db820c: add missing regulator detailsDmitry Baryshkov1-0/+5
Specify that S11 (well, whole block of s8+s9+s10+s11) of pm8994 and S2 (s2 + s3) of pmi8994 are supplied by vph_pwr. While we are at it, add regulator name to S11, so that is displayed as VDD_APCC in the system. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211104002949.2204727-2-dmitry.baryshkov@linaro.org
2021-11-20arm64: dts: qcom: apq8096-db820c: specify adsp firmware nameDmitry Baryshkov1-0/+1
Specify firmware name to be used for the ADSP. Quoting Bjorn from the respective apq8016-sbc commit: The firmware for the modem and WiFi subsystems platform specific and is signed with a OEM specific key (or a test key). In order to support more than a single device it is therefor not possible to rely on the default path and stash these files directly in the firmware directory. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211104002949.2204727-1-dmitry.baryshkov@linaro.org
2021-11-20arm64: dts: qcom: Add support for SONY Xperia XZ2 / XZ2C / XZ3 (Tama platform)Konrad Dybcio5-0/+496
Add support for SONY Xperia XZ2, XZ2 Compact and XZ3 smartphones, all based on the Qualcomm SDM845 chipset. There also exists a fourth Tama device, the XZ2 Premium (Aurora) with a 4K display, but it's relatively rare. The devices are affected by a scary UFS behaviour where sending a certain UFS command (which is worked around on downstream) renders the device unbootable, by effectively erasing the bootloader. Therefore UFS AND UFSPHY are strictly disabled for now. Downstream workaround: https://github.com/kholk/kernel/commit/2e7a9ee1c91a016baa0b826a7752ec45663a0561 This platform's bootloader is not very nice either. To boot mainline you need to flash a bogus DTBO (fastboot erasing may cut it, but it takes an inhumane amount of time) - one that's just 4 bytes (all zeroes) seems to work just fine. Of course, one can also provide a "normal" DTBO (device-specific DT overlayed on top of the SoC DT), but that's not yet supported by the mainline kernel build system. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211111184630.605035-1-konrad.dybcio@somainline.org
2021-11-20arm64: dts: qcom: msm8996: drop not documented adreno propertiesDavid Heidelberg1-3/+0
These properties aren't documented nor implemented in the driver. Drop them. Fixes warnings as: $ make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/display/msm/gpu.yaml ... arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml: gpu@b00000: 'qcom,gpu-quirk-fault-detect-mask', 'qcom,gpu-quirk-two-pass-use-wfi' do not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/display/msm/gpu.yaml ... Fixes: 69cc3114ab0f ("arm64: dts: Add Adreno GPU definitions") Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211030100413.28370-1-david@ixit.cz
2021-11-20arm64: dts: qcom: sc7180: Support Homestar rev4Philip Chen5-5/+24
Support Homestar rev4 board where Parade ps8640 is added as the second source edp bridge. Support different edp bridge chips in different board revisions, now we move the #incldue line of the edp bridge dts fragment (e.g. sc7180-trogdor-ti-sn65dsi86.dtsi) from "sc7180-trogdor-homestar.dtsi" to per-board-rev dts files. Since the edp bridge dts fragment overrides 'dsi0_out', which is defined in "sc7180.dtsi", move the #incldue line of "sc7180.dtsi" from "sc7180-trogdor-homestar.dtsi" to per-board-rev dts files too, before the #include line of the edp bridge dts fragment. Signed-off-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211029152647.v3.4.If7aaa8e36f1269acae5488035bd62ce543756bf8@changeid
2021-11-20arm64: dts: qcom: sc7180: Support Lazor/Limozeen rev9Philip Chen15-17/+188
Support Lazor/Limozeen rev9 board where Parade ps8640 is added as the second source edp bridge. To support different edp bridge chips in different board revisions, now we move the #incldue line of the edp bridge dts fragment (e.g. sc7180-trogdor-ti-sn65dsi86.dtsi) from "sc7180-trogdor-lazor.dtsi" to per-board-rev dts files. Since the edp bridge dts fragment overrides 'dsi0_out', which is defined in "sc7180.dtsi", move the #incldue line of "sc7180.dtsi" from "sc7180-trogdor-lazor.dtsi" to per-board-rev dts files too, before the #include line of the edp bridge dts fragment. Signed-off-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211029152647.v3.3.Ie56f55924f5c7706fe3194e710bbef6fdb8b5bc6@changeid
2021-11-20arm64: dts: qcom: sc7180: Specify "data-lanes" for DSI host outputPhilip Chen2-1/+4
MSM DSI host driver actually parses "data-lanes" in DT and compare it with the number of DSI lanes the bridge driver sets for mipi_dsi_device. So we need to always specify "data-lanes" for the DSI host output. As of now, "data-lanes" is added to ti-sn65dsi86 dts fragment, but missing in parade-ps8640 dts fragment, which requires a fixup. Since we'll do 4-lane DSI regardless of which bridge chip is used, instead of adding "data-lanes" to parade-ps8640 dts fragment, let's just move "data-lanes" from the bridge dts to sc7180-trogdor.dtsi. Signed-off-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211029152647.v3.2.If23c83a786fc4d318a1986f43803f22b4b1d82cd@changeid
2021-11-20arm64: dts: qcom: sc7180: Include gpio.h in edp bridge dtsPhilip Chen2-0/+4
The edp bridge dts fragment files use the macros defined in 'dt-bindings/gpio/gpio.h'. To help us more flexibly order the #include lines of dts files in a board-revision-specific dts file, let's include the gpio header in the bridge dts fragment files themselves. Signed-off-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211029152647.v3.1.Ie17e51ad3eb91d72826ce651ca2786534a360210@changeid
2021-11-17arm64: dts: qcom: ipq8074: add MDIO busRobert Marko1-0/+12
IPQ8074 uses an IPQ4019 compatible MDIO controller that is already supported in the kernel, so add the DT node in order to use it. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211007115846.26255-1-robimarko@gmail.com
2021-11-17arm64: dts: qcom: sdm845-xiaomi-beryllium: set venus firmware pathKate Doeen1-0/+1
Enable loading the Qualcomm Venus video accelerator firmware on Xiaomi Pocophone F1. Signed-off-by: Kate Doeen <jld3103yt@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211028102016.106063-1-jld3103yt@gmail.com
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