aboutsummaryrefslogtreecommitdiffstats
path: root/tools/perf/scripts/python/syscall-counts-by-pid.py (unfollow)
AgeCommit message (Collapse)AuthorFilesLines
2012-07-20ARM: LPC32xx: Set system serial based on cpu unique idAlexandre Pereira da Silva1-2/+8
LPC32xx SoC has a 128 bits unique id that can be used as a system serial number, if none has been provided by atags or dt. Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-07-12ARM: LPC32xx: Adjust to pl08x DMA interface changesRoland Stigge1-4/+3
This patch adjusts the LPC32xx platform support to the new pl08x DMA interface, fixing the compile error resulting from changed pl08x structures. Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-07-01ARM: LPC32xx: Remove unused gpiosAlexandre Pereira da Silva1-3/+0
Remove SPI0_CS, MMC_CD and MMC_WP gpios as they moved to devicetree. Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-07-01ARM: LPC32xx: Remove USB and I2C init from phy3250.cRoland Stigge1-12/+0
USB and I2C initialization can be removed safely from the board specific phy3250.c, now that initialization moved to the generalized clock.c. Signed-off-by: Roland Stigge <stigge@antcom.de> Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-07-01ARM: LPC32xx: Cleanup USB clock initAlexandre Pereira da Silva2-1/+81
Move most of usb clock initialization from lpc32xx_udc and ohci-nxp to clock.c. Also adds ohci clocks and otg clocks. Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-07-01ARM: LPC32xx: Remove wrong re-initialization of MMC clock registerRoland Stigge1-7/+3
This patch fixes a bug, (wrongfully) resetting the value of LPC32XX_CLKPWR_MS_CTRL back to its initial contents (after careful setup). This was discovered only with a board/bootloader combination (EA3250) where the contents of the respective register wasn't already at the correct value on Linux boot. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-07-01ARM: LPC32xx: Add further bits to MMC initRoland Stigge1-1/+5
This patch makes sure certain MMC bits are cleared as they should for initialization. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-07-01ARM: LPC32xx: Init MMC via clockRoland Stigge2-7/+4
This patch moves MMC/SD controller initialization from the board specific file phy3250.c to clock.c. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: Move i2s1 dma enabling to clock.cAlexandre Pereira da Silva2-6/+2
Move i2s1 dma init to be done when it's clock is enabled. Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Move uart6 irda disable to serial.cAlexandre Pereira da Silva2-5/+5
Move the irda configuration to serial.c where other special cases are handled Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Cleanup board init, remove duplicate clock initAlexandre Pereira da Silva1-17/+0
Remove SSP0, CLCD and DMA clocks that are already migrated to the clock framework. Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Remove spi chip definitionsAlexandre Pereira da Silva1-56/+0
Leave chipselect and spi devices binding to the devicetree Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Remove spi chipselect request from board initAlexandre Pereira da Silva1-7/+0
The lpc32xx spi0 chipselect will be requested directly from the pl022 driver Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Add dt settings to the at25 nodeAlexandre Pereira da Silva1-0/+21
Add the reg, cs-gpios and max-frequencies that are needed for spi device registry in phy3250. Adds also the pl022 internal transfers details via dt Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Build arch dtbsAlexandre Pereira da Silva1-0/+1
Add ea3250.dtb and phy3250.dtb to the list of dtbs to be built Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Fix lpc32xx.dtsi status property: "disable" -> "disabled"Roland Stigge1-7/+7
This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Remove mach specific ARCH_NR_GPIOS, use defaultRoland Stigge1-2/+0
ARCH_NR_GPIOS was defined statically to include exactly all SoC specific GPIOs. Now if additional GPIOs need to be added dynamically, e.g. via DT, none are available. Removing the mach specific setting, leaving ARCH_NR_GPIOS to the default of 256 (currently in include/asm-generic/gpio.h). Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: High Speed UART configuration via DTRoland Stigge2-5/+15
This patch fixes the DTS files for the High Speed UARTs 1, 2 and 7 of the LPC32xx SoC, adjusting the compatible strings, adding interrupts and status configuration. On the PHY3250 reference board, UART2 is enabled. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: DT conversion of Standard UARTsRoland Stigge5-126/+35
This patch switches from static serial driver initialization to devicetree configuration. This way, the Standard UARTs of the LPC32xx SoC can be enabled individually via DT. E.g., instead of Kconfig configuration, the phy3250.dts activates UARTs 3 and 5. Signed-off-by: Roland Stigge <stigge@antcom.de> Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: DTS adjustment for using pl18x primecellRoland Stigge2-1/+10
This patch adjusts the dts files to reference the pl18x primecell driver correctly. Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Add MMC controller supportRoland Stigge1-4/+39
This patch adds support for the MMC controller of the LPC32xx SoC to the platform initialization via the pl08x primecell driver. Lacking more complete DT support, done via DT auxdata. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: Defconfig updateRoland Stigge1-6/+18
This defconfig update for the LPC32xx SoC platform adds the new drivers in v3.5 and drivers typically used in systems with the LPC32xx chip. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: Clock adjustment for key matrix controllerRoland Stigge1-1/+1
The clock.c file needs to be changed to match the automatic device name to its clock. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com>
2012-06-14ARM: LPC32xx: DTS adjustment for key matrix controllerRoland Stigge2-0/+11
This patch connects the lpc32xx-key driver to the LPC32xx platform (via lpc32xx.dtsi), and more specifically to the reference board via its dts file. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>