From 4973ddc8426405ebe71c48bd3d5e20d83877c076 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 14 Oct 2019 12:51:04 +0300 Subject: pinctrl: intel: Avoid potential glitches if pin is in GPIO mode When consumer requests a pin, in order to be on the safest side, we switch it first to GPIO mode followed by immediate transition to the input state. Due to posted writes it's luckily to be a single I/O transaction. However, if firmware or boot loader already configures the pin to the GPIO mode, user expects no glitches for the requested pin. We may check if the pin is pre-configured and leave it as is till the actual consumer toggles its state to avoid glitches. Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support") Depends-on: f5a26acf0162 ("pinctrl: intel: Initialize GPIO properly when used through irqchip") Cc: stable@vger.kernel.org Cc: fei.yang@intel.com Reported-by: Oliver Barta Reported-by: Malin Jonsson Signed-off-by: Andy Shevchenko Signed-off-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index bc013599a9a3..83981ad66a71 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -52,6 +52,7 @@ #define PADCFG0_GPIROUTNMI BIT(17) #define PADCFG0_PMODE_SHIFT 10 #define PADCFG0_PMODE_MASK GENMASK(13, 10) +#define PADCFG0_PMODE_GPIO 0 #define PADCFG0_GPIORXDIS BIT(9) #define PADCFG0_GPIOTXDIS BIT(8) #define PADCFG0_GPIORXSTATE BIT(1) @@ -332,7 +333,7 @@ static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; - if (!mode) + if (mode == PADCFG0_PMODE_GPIO) seq_puts(s, "GPIO "); else seq_printf(s, "mode %d ", mode); @@ -458,6 +459,11 @@ static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) writel(value, padcfg0); } +static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) +{ + return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; +} + static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) { u32 value; @@ -491,7 +497,20 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, } padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); + + /* + * If pin is already configured in GPIO mode, we assume that + * firmware provides correct settings. In such case we avoid + * potential glitches on the pin. Otherwise, for the pin in + * alternative mode, consumer has to supply respective flags. + */ + if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) { + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + return 0; + } + intel_gpio_set_gpio_mode(padcfg0); + /* Disable TX buffer and enable RX (this will be input) */ __intel_gpio_set_direction(padcfg0, true); -- cgit v1.2.3-59-g8ed1b From 3739898576a13a41e319cf7d875cb68b9d9d35cc Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 18 Oct 2019 11:08:42 +0200 Subject: pinctrl: cherryview: Fix irq_valid_mask calculation Commit 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation") has made the cherryview gpio numbers sparse, to get a 1:1 mapping between ACPI pin numbers and gpio numbers in Linux. This has greatly simplified things, but the code setting the irq_valid_mask was not updated for this, so the valid mask is still in the old "compressed" numbering with the gaps in the pin numbers skipped, which is wrong as irq_valid_mask needs to be expressed in gpio numbers. This results in the following error on devices using pin 24 (0x0018) on the north GPIO controller as an ACPI event source: [ 0.422452] cherryview-pinctrl INT33FF:01: Failed to translate GPIO to IRQ This has been reported (by email) to be happening on a Caterpillar CAT T20 tablet and I've reproduced this myself on a Medion Akoya e2215t 2-in-1. This commit uses the pin number instead of the compressed index into community->pins to clear the correct bits in irq_valid_mask for GPIOs using GPEs for interrupts, fixing these errors and in case of the Medion Akoya e2215t also fixing the LID switch not working. Cc: stable@vger.kernel.org Fixes: 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation") Signed-off-by: Hans de Goede Reviewed-by: Andy Shevchenko Signed-off-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index c6251eac8946..c31266e70559 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1559,7 +1559,7 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip, intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; if (intsel >= community->nirqs) - clear_bit(i, valid_mask); + clear_bit(desc->number, valid_mask); } } -- cgit v1.2.3-59-g8ed1b From 17d49c6258e6aa43981c0e3bcf94091af17b607b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 23 Oct 2019 16:32:03 +0300 Subject: pinctrl: cherryview: Fix spelling mistake in the comment One spelling mistake is being fixed: benerate -> generate. It is a complimentary fix to the commit 505485a83c55 ("pinctrl: cherryview fixed typo in comment"). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index c31266e70559..5af6b20f7334 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -377,7 +377,7 @@ static const struct chv_community southwest_community = { .gpio_ranges = southwest_gpio_ranges, .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), /* - * Southwest community can benerate GPIO interrupts only for the + * Southwest community can generate GPIO interrupts only for the * first 8 interrupts. The upper half (8-15) can only be used to * trigger GPEs. */ -- cgit v1.2.3-59-g8ed1b From e58e177392b9df5699373f7fee1329a7145b0c88 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 24 Oct 2019 16:34:41 +0300 Subject: pinctrl: cherryview: Allocate IRQ chip dynamic Keeping the IRQ chip definition static shares it with multiple instances of the GPIO chip in the system. This is bad and now we get this warning from GPIO library: "detected irqchip that is shared with multiple gpiochips: please fix the driver." Hence, move the IRQ chip definition from being driver static into the struct intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance. This patch is heavily based on the attachment to the bug by Christoph Marz. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=202543 Fixes: 6e08d6bbebeb ("pinctrl: Add Intel Cherryview/Braswell pin controller support") Depends-on: 83b9dc11312f ("pinctrl: cherryview: Associate IRQ descriptors to irqdomain") Signed-off-by: Andy Shevchenko Signed-off-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 5af6b20f7334..dff2a81250b6 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -147,6 +147,7 @@ struct chv_pin_context { * @pctldesc: Pin controller description * @pctldev: Pointer to the pin controller device * @chip: GPIO chip in this pin controller + * @irqchip: IRQ chip in this pin controller * @regs: MMIO registers * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO * offset (in GPIO number space) @@ -162,6 +163,7 @@ struct chv_pinctrl { struct pinctrl_desc pctldesc; struct pinctrl_dev *pctldev; struct gpio_chip chip; + struct irq_chip irqchip; void __iomem *regs; unsigned intr_lines[16]; const struct chv_community *community; @@ -1466,16 +1468,6 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) return 0; } -static struct irq_chip chv_gpio_irqchip = { - .name = "chv-gpio", - .irq_startup = chv_gpio_irq_startup, - .irq_ack = chv_gpio_irq_ack, - .irq_mask = chv_gpio_irq_mask, - .irq_unmask = chv_gpio_irq_unmask, - .irq_set_type = chv_gpio_irq_type, - .flags = IRQCHIP_SKIP_SET_WAKE, -}; - static void chv_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); @@ -1625,7 +1617,15 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) } } - ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, + pctrl->irqchip.name = "chv-gpio"; + pctrl->irqchip.irq_startup = chv_gpio_irq_startup; + pctrl->irqchip.irq_ack = chv_gpio_irq_ack; + pctrl->irqchip.irq_mask = chv_gpio_irq_mask; + pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask; + pctrl->irqchip.irq_set_type = chv_gpio_irq_type; + pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE; + + ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0, handle_bad_irq, IRQ_TYPE_NONE); if (ret) { dev_err(pctrl->dev, "failed to add IRQ chip\n"); @@ -1642,7 +1642,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) } } - gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, + gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq, chv_gpio_irq_handler); return 0; } -- cgit v1.2.3-59-g8ed1b From f78f152a1a3f09c4f0b2bbe4d80a22e44e541d42 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 22 Oct 2019 13:00:00 +0300 Subject: pinctrl: intel: Introduce intel_restore_padcfg() helper Deduplicate restoring PADCFGx registers by using a common helper. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 51 +++++++++++++++++------------------ 1 file changed, 24 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 83981ad66a71..181e5c8c1855 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1607,6 +1607,27 @@ intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value) return curr; } +static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, + unsigned int reg, u32 saved) +{ + u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0; + unsigned int n = reg / sizeof(u32); + struct device *dev = pctrl->dev; + void __iomem *padcfg; + u32 value; + + padcfg = intel_get_padcfg(pctrl, pin, reg); + if (!padcfg) + return; + + value = readl(padcfg) & ~mask; + if (value == saved) + return; + + writel(saved, padcfg); + dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg)); +} + int intel_pinctrl_resume_noirq(struct device *dev) { struct intel_pinctrl *pctrl = dev_get_drvdata(dev); @@ -1620,37 +1641,13 @@ int intel_pinctrl_resume_noirq(struct device *dev) pads = pctrl->context.pads; for (i = 0; i < pctrl->soc->npins; i++) { const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; - void __iomem *padcfg; - u32 val; if (!intel_pinctrl_should_save(pctrl, desc->number)) continue; - padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); - val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; - if (val != pads[i].padcfg0) { - writel(pads[i].padcfg0, padcfg); - dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", - desc->number, readl(padcfg)); - } - - padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); - val = readl(padcfg); - if (val != pads[i].padcfg1) { - writel(pads[i].padcfg1, padcfg); - dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", - desc->number, readl(padcfg)); - } - - padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); - if (padcfg) { - val = readl(padcfg); - if (val != pads[i].padcfg2) { - writel(pads[i].padcfg2, padcfg); - dev_dbg(dev, "restored pin %u padcfg2 %#08x\n", - desc->number, readl(padcfg)); - } - } + intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); + intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); + intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); } communities = pctrl->context.communities; -- cgit v1.2.3-59-g8ed1b From 7101e022523bfb269bdedbc874ca5d44508420ca Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 22 Oct 2019 13:00:01 +0300 Subject: pinctrl: intel: Introduce intel_restore_hostown() helper Refactor restoring HOSTSW_OWN registers by using an introduced helper. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 38 +++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 181e5c8c1855..1bdc0365e1ad 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1607,6 +1607,25 @@ intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value) return curr; } +static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, + void __iomem *base, unsigned int gpp, u32 saved) +{ + const struct intel_community *community = &pctrl->communities[c]; + const struct intel_padgroup *padgrp = &community->gpps[gpp]; + struct device *dev = pctrl->dev; + u32 requested, value; + + if (padgrp->gpio_base < 0) + return; + + requested = intel_gpio_is_requested(&pctrl->chip, padgrp->gpio_base, padgrp->size); + value = intel_gpio_update_pad_mode(base + gpp * 4, requested, saved); + if (!((value ^ saved) & requested)) + return; + + dev_warn(dev, "restored hostown %u/%u %#8x->%#8x\n", c, gpp, value, saved); +} + static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int reg, u32 saved) { @@ -1664,23 +1683,8 @@ int intel_pinctrl_resume_noirq(struct device *dev) } base = community->regs + community->hostown_offset; - for (gpp = 0; gpp < community->ngpps; gpp++) { - const struct intel_padgroup *padgrp = &community->gpps[gpp]; - u32 requested = 0, value = 0; - u32 saved = communities[i].hostown[gpp]; - - if (padgrp->gpio_base < 0) - continue; - - requested = intel_gpio_is_requested(&pctrl->chip, - padgrp->gpio_base, padgrp->size); - value = intel_gpio_update_pad_mode(base + gpp * 4, - requested, saved); - if ((value ^ saved) & requested) { - dev_warn(dev, "restore hostown %d/%u %#8x->%#8x\n", - i, gpp, value, saved); - } - } + for (gpp = 0; gpp < community->ngpps; gpp++) + intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]); } return 0; -- cgit v1.2.3-59-g8ed1b From 471dd9a9c7c197b143f1aca05a31e385115986b0 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 22 Oct 2019 13:00:02 +0300 Subject: pinctrl: intel: Introduce intel_restore_intmask() helper Refactor restoring GPI_IE registers by using an introduced helper. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 1bdc0365e1ad..da34750a420f 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1626,6 +1626,15 @@ static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, dev_warn(dev, "restored hostown %u/%u %#8x->%#8x\n", c, gpp, value, saved); } +static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, + void __iomem *base, unsigned int gpp, u32 saved) +{ + struct device *dev = pctrl->dev; + + writel(saved, base + gpp * 4); + dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); +} + static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int reg, u32 saved) { @@ -1676,11 +1685,8 @@ int intel_pinctrl_resume_noirq(struct device *dev) unsigned int gpp; base = community->regs + community->ie_offset; - for (gpp = 0; gpp < community->ngpps; gpp++) { - writel(communities[i].intmask[gpp], base + gpp * 4); - dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, - readl(base + gpp * 4)); - } + for (gpp = 0; gpp < community->ngpps; gpp++) + intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]); base = community->regs + community->hostown_offset; for (gpp = 0; gpp < community->ngpps; gpp++) -- cgit v1.2.3-59-g8ed1b From 764cfe33517f7cda42f01bb5e4077cfce2233230 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 22 Oct 2019 13:00:03 +0300 Subject: pinctrl: intel: Drop level from warning to debug in intel_restore_hostown() Since we didn't get any new reports from users about wrong settings of pad ownership, there is no point to spam kernel log with it. Thus, drop level from warning to debug. Also, modify format to be in align with the rest restore helpers. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index da34750a420f..54a5eb33c9fa 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1623,7 +1623,7 @@ static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, if (!((value ^ saved) & requested)) return; - dev_warn(dev, "restored hostown %u/%u %#8x->%#8x\n", c, gpp, value, saved); + dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); } static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, -- cgit v1.2.3-59-g8ed1b From 942c5ea49ffbe28b004ffb9b620f1aa4e21ba94a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 22 Oct 2019 13:00:04 +0300 Subject: pinctrl: intel: Use helper to restore register values on ->resume() We can restore only values that had been changed and do not spam kernel log with unnecessary messages. Convert intel_gpio_update_pad_mode() to a helper function that will be used across few callers. Suggested-by: Mika Westerberg Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 54a5eb33c9fa..b54b27228ad9 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1595,16 +1595,18 @@ intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size) return requested; } -static u32 -intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value) +static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value) { u32 curr, updated; - curr = readl(hostown); + curr = readl(reg); + updated = (curr & ~mask) | (value & mask); - writel(updated, hostown); + if (curr == updated) + return false; - return curr; + writel(updated, reg); + return true; } static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, @@ -1613,14 +1615,13 @@ static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, const struct intel_community *community = &pctrl->communities[c]; const struct intel_padgroup *padgrp = &community->gpps[gpp]; struct device *dev = pctrl->dev; - u32 requested, value; + u32 requested; if (padgrp->gpio_base < 0) return; requested = intel_gpio_is_requested(&pctrl->chip, padgrp->gpio_base, padgrp->size); - value = intel_gpio_update_pad_mode(base + gpp * 4, requested, saved); - if (!((value ^ saved) & requested)) + if (!intel_gpio_update_reg(base + gpp * 4, requested, saved)) return; dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); @@ -1631,7 +1632,9 @@ static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, { struct device *dev = pctrl->dev; - writel(saved, base + gpp * 4); + if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved)) + return; + dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); } @@ -1642,17 +1645,14 @@ static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int n = reg / sizeof(u32); struct device *dev = pctrl->dev; void __iomem *padcfg; - u32 value; padcfg = intel_get_padcfg(pctrl, pin, reg); if (!padcfg) return; - value = readl(padcfg) & ~mask; - if (value == saved) + if (!intel_gpio_update_reg(padcfg, ~mask, saved)) return; - writel(saved, padcfg); dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg)); } -- cgit v1.2.3-59-g8ed1b From c9ccf71fc8073b8d3a484751585088ff14c8d762 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 21 Oct 2019 19:45:28 +0300 Subject: pinctrl: intel: Add Intel Tiger Lake pin controller support This driver adds pinctrl/GPIO support for Intel Tiger Lake SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Signed-off-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/Kconfig | 7 + drivers/pinctrl/intel/Makefile | 1 + drivers/pinctrl/intel/pinctrl-tigerlake.c | 454 ++++++++++++++++++++++++++++++ 3 files changed, 462 insertions(+) create mode 100644 drivers/pinctrl/intel/pinctrl-tigerlake.c diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index 452a14f78707..6091947a8f51 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -115,4 +115,11 @@ config PINCTRL_SUNRISEPOINT provides an interface that allows configuring of PCH pins and using them as GPIOs. +config PINCTRL_TIGERLAKE + tristate "Intel Tiger Lake pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Tiger Lake PCH pins and using them as GPIOs. endif diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index cb491e655749..7e620b471ef6 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o +obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c new file mode 100644 index 000000000000..58572b15b3ce --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Tiger Lake PCH pinctrl/GPIO driver + * + * Copyright (C) 2019, Intel Corporation + * Authors: Andy Shevchenko + * Mika Westerberg + */ + +#include +#include +#include + +#include + +#include "pinctrl-intel.h" + +#define TGL_PAD_OWN 0x020 +#define TGL_PADCFGLOCK 0x080 +#define TGL_HOSTSW_OWN 0x0b0 +#define TGL_GPI_IS 0x100 +#define TGL_GPI_IE 0x120 + +#define TGL_GPP(r, s, e) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + } + +#define TGL_COMMUNITY(s, e, g) \ + { \ + .padown_offset = TGL_PAD_OWN, \ + .padcfglock_offset = TGL_PADCFGLOCK, \ + .hostown_offset = TGL_HOSTSW_OWN, \ + .is_offset = TGL_GPI_IS, \ + .ie_offset = TGL_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ + } + +/* Tiger Lake-LP */ +static const struct pinctrl_pin_desc tgllp_community0_pins[] = { + /* GPP_B */ + PINCTRL_PIN(0, "CORE_VID_0"), + PINCTRL_PIN(1, "CORE_VID_1"), + PINCTRL_PIN(2, "VRALERTB"), + PINCTRL_PIN(3, "CPU_GP_2"), + PINCTRL_PIN(4, "CPU_GP_3"), + PINCTRL_PIN(5, "ISH_I2C0_SDA"), + PINCTRL_PIN(6, "ISH_I2C0_SCL"), + PINCTRL_PIN(7, "ISH_I2C1_SDA"), + PINCTRL_PIN(8, "ISH_I2C1_SCL"), + PINCTRL_PIN(9, "I2C5_SDA"), + PINCTRL_PIN(10, "I2C5_SCL"), + PINCTRL_PIN(11, "PMCALERTB"), + PINCTRL_PIN(12, "SLP_S0B"), + PINCTRL_PIN(13, "PLTRSTB"), + PINCTRL_PIN(14, "SPKR"), + PINCTRL_PIN(15, "GSPI0_CS0B"), + PINCTRL_PIN(16, "GSPI0_CLK"), + PINCTRL_PIN(17, "GSPI0_MISO"), + PINCTRL_PIN(18, "GSPI0_MOSI"), + PINCTRL_PIN(19, "GSPI1_CS0B"), + PINCTRL_PIN(20, "GSPI1_CLK"), + PINCTRL_PIN(21, "GSPI1_MISO"), + PINCTRL_PIN(22, "GSPI1_MOSI"), + PINCTRL_PIN(23, "SML1ALERTB"), + PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"), + /* GPP_T */ + PINCTRL_PIN(26, "I2C6_SDA"), + PINCTRL_PIN(27, "I2C6_SCL"), + PINCTRL_PIN(28, "I2C7_SDA"), + PINCTRL_PIN(29, "I2C7_SCL"), + PINCTRL_PIN(30, "UART4_RXD"), + PINCTRL_PIN(31, "UART4_TXD"), + PINCTRL_PIN(32, "UART4_RTSB"), + PINCTRL_PIN(33, "UART4_CTSB"), + PINCTRL_PIN(34, "UART5_RXD"), + PINCTRL_PIN(35, "UART5_TXD"), + PINCTRL_PIN(36, "UART5_RTSB"), + PINCTRL_PIN(37, "UART5_CTSB"), + PINCTRL_PIN(38, "UART6_RXD"), + PINCTRL_PIN(39, "UART6_TXD"), + PINCTRL_PIN(40, "UART6_RTSB"), + PINCTRL_PIN(41, "UART6_CTSB"), + /* GPP_A */ + PINCTRL_PIN(42, "ESPI_IO_0"), + PINCTRL_PIN(43, "ESPI_IO_1"), + PINCTRL_PIN(44, "ESPI_IO_2"), + PINCTRL_PIN(45, "ESPI_IO_3"), + PINCTRL_PIN(46, "ESPI_CSB"), + PINCTRL_PIN(47, "ESPI_CLK"), + PINCTRL_PIN(48, "ESPI_RESETB"), + PINCTRL_PIN(49, "I2S2_SCLK"), + PINCTRL_PIN(50, "I2S2_SFRM"), + PINCTRL_PIN(51, "I2S2_TXD"), + PINCTRL_PIN(52, "I2S2_RXD"), + PINCTRL_PIN(53, "PMC_I2C_SDA"), + PINCTRL_PIN(54, "SATAXPCIE_1"), + PINCTRL_PIN(55, "PMC_I2C_SCL"), + PINCTRL_PIN(56, "USB2_OCB_1"), + PINCTRL_PIN(57, "USB2_OCB_2"), + PINCTRL_PIN(58, "USB2_OCB_3"), + PINCTRL_PIN(59, "DDSP_HPD_C"), + PINCTRL_PIN(60, "DDSP_HPD_B"), + PINCTRL_PIN(61, "DDSP_HPD_1"), + PINCTRL_PIN(62, "DDSP_HPD_2"), + PINCTRL_PIN(63, "GPPC_A_21"), + PINCTRL_PIN(64, "GPPC_A_22"), + PINCTRL_PIN(65, "I2S1_SCLK"), + PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), +}; + +static const struct intel_padgroup tgllp_community0_gpps[] = { + TGL_GPP(0, 0, 25), /* GPP_B */ + TGL_GPP(1, 26, 41), /* GPP_T */ + TGL_GPP(2, 42, 66), /* GPP_A */ +}; + +static const struct intel_community tgllp_community0[] = { + TGL_COMMUNITY(0, 66, tgllp_community0_gpps), +}; + +static const struct intel_pinctrl_soc_data tgllp_community0_soc_data = { + .uid = "0", + .pins = tgllp_community0_pins, + .npins = ARRAY_SIZE(tgllp_community0_pins), + .communities = tgllp_community0, + .ncommunities = ARRAY_SIZE(tgllp_community0), +}; + +static const struct pinctrl_pin_desc tgllp_community1_pins[] = { + /* GPP_S */ + PINCTRL_PIN(0, "SNDW0_CLK"), + PINCTRL_PIN(1, "SNDW0_DATA"), + PINCTRL_PIN(2, "SNDW1_CLK"), + PINCTRL_PIN(3, "SNDW1_DATA"), + PINCTRL_PIN(4, "SNDW2_CLK"), + PINCTRL_PIN(5, "SNDW2_DATA"), + PINCTRL_PIN(6, "SNDW3_CLK"), + PINCTRL_PIN(7, "SNDW3_DATA"), + /* GPP_H */ + PINCTRL_PIN(8, "GPPC_H_0"), + PINCTRL_PIN(9, "GPPC_H_1"), + PINCTRL_PIN(10, "GPPC_H_2"), + PINCTRL_PIN(11, "SX_EXIT_HOLDOFFB"), + PINCTRL_PIN(12, "I2C2_SDA"), + PINCTRL_PIN(13, "I2C2_SCL"), + PINCTRL_PIN(14, "I2C3_SDA"), + PINCTRL_PIN(15, "I2C3_SCL"), + PINCTRL_PIN(16, "I2C4_SDA"), + PINCTRL_PIN(17, "I2C4_SCL"), + PINCTRL_PIN(18, "SRCCLKREQB_4"), + PINCTRL_PIN(19, "SRCCLKREQB_5"), + PINCTRL_PIN(20, "M2_SKT2_CFG_0"), + PINCTRL_PIN(21, "M2_SKT2_CFG_1"), + PINCTRL_PIN(22, "M2_SKT2_CFG_2"), + PINCTRL_PIN(23, "M2_SKT2_CFG_3"), + PINCTRL_PIN(24, "DDPB_CTRLCLK"), + PINCTRL_PIN(25, "DDPB_CTRLDATA"), + PINCTRL_PIN(26, "CPU_C10_GATEB"), + PINCTRL_PIN(27, "TIME_SYNC_0"), + PINCTRL_PIN(28, "IMGCLKOUT_1"), + PINCTRL_PIN(29, "IMGCLKOUT_2"), + PINCTRL_PIN(30, "IMGCLKOUT_3"), + PINCTRL_PIN(31, "IMGCLKOUT_4"), + /* GPP_D */ + PINCTRL_PIN(32, "ISH_GP_0"), + PINCTRL_PIN(33, "ISH_GP_1"), + PINCTRL_PIN(34, "ISH_GP_2"), + PINCTRL_PIN(35, "ISH_GP_3"), + PINCTRL_PIN(36, "IMGCLKOUT_0"), + PINCTRL_PIN(37, "SRCCLKREQB_0"), + PINCTRL_PIN(38, "SRCCLKREQB_1"), + PINCTRL_PIN(39, "SRCCLKREQB_2"), + PINCTRL_PIN(40, "SRCCLKREQB_3"), + PINCTRL_PIN(41, "ISH_SPI_CSB"), + PINCTRL_PIN(42, "ISH_SPI_CLK"), + PINCTRL_PIN(43, "ISH_SPI_MISO"), + PINCTRL_PIN(44, "ISH_SPI_MOSI"), + PINCTRL_PIN(45, "ISH_UART0_RXD"), + PINCTRL_PIN(46, "ISH_UART0_TXD"), + PINCTRL_PIN(47, "ISH_UART0_RTSB"), + PINCTRL_PIN(48, "ISH_UART0_CTSB"), + PINCTRL_PIN(49, "ISH_GP_4"), + PINCTRL_PIN(50, "ISH_GP_5"), + PINCTRL_PIN(51, "I2S_MCLK1_OUT"), + PINCTRL_PIN(52, "GSPI2_CLK_LOOPBK"), + /* GPP_U */ + PINCTRL_PIN(53, "UART3_RXD"), + PINCTRL_PIN(54, "UART3_TXD"), + PINCTRL_PIN(55, "UART3_RTSB"), + PINCTRL_PIN(56, "UART3_CTSB"), + PINCTRL_PIN(57, "GSPI3_CS0B"), + PINCTRL_PIN(58, "GSPI3_CLK"), + PINCTRL_PIN(59, "GSPI3_MISO"), + PINCTRL_PIN(60, "GSPI3_MOSI"), + PINCTRL_PIN(61, "GSPI4_CS0B"), + PINCTRL_PIN(62, "GSPI4_CLK"), + PINCTRL_PIN(63, "GSPI4_MISO"), + PINCTRL_PIN(64, "GSPI4_MOSI"), + PINCTRL_PIN(65, "GSPI5_CS0B"), + PINCTRL_PIN(66, "GSPI5_CLK"), + PINCTRL_PIN(67, "GSPI5_MISO"), + PINCTRL_PIN(68, "GSPI5_MOSI"), + PINCTRL_PIN(69, "GSPI6_CS0B"), + PINCTRL_PIN(70, "GSPI6_CLK"), + PINCTRL_PIN(71, "GSPI6_MISO"), + PINCTRL_PIN(72, "GSPI6_MOSI"), + PINCTRL_PIN(73, "GSPI3_CLK_LOOPBK"), + PINCTRL_PIN(74, "GSPI4_CLK_LOOPBK"), + PINCTRL_PIN(75, "GSPI5_CLK_LOOPBK"), + PINCTRL_PIN(76, "GSPI6_CLK_LOOPBK"), + /* vGPIO */ + PINCTRL_PIN(77, "CNV_BTEN"), + PINCTRL_PIN(78, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(79, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(80, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(81, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(82, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(83, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(84, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(85, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(86, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(87, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(88, "vUART0_TXD"), + PINCTRL_PIN(89, "vUART0_RXD"), + PINCTRL_PIN(90, "vUART0_CTS_B"), + PINCTRL_PIN(91, "vUART0_RTS_B"), + PINCTRL_PIN(92, "vISH_UART0_TXD"), + PINCTRL_PIN(93, "vISH_UART0_RXD"), + PINCTRL_PIN(94, "vISH_UART0_CTS_B"), + PINCTRL_PIN(95, "vISH_UART0_RTS_B"), + PINCTRL_PIN(96, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(97, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(98, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(99, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(100, "vI2S2_SCLK"), + PINCTRL_PIN(101, "vI2S2_SFRM"), + PINCTRL_PIN(102, "vI2S2_TXD"), + PINCTRL_PIN(103, "vI2S2_RXD"), +}; + +static const struct intel_padgroup tgllp_community1_gpps[] = { + TGL_GPP(0, 0, 7), /* GPP_S */ + TGL_GPP(1, 8, 31), /* GPP_H */ + TGL_GPP(2, 32, 52), /* GPP_D */ + TGL_GPP(3, 53, 76), /* GPP_U */ + TGL_GPP(4, 77, 103), /* vGPIO */ +}; + +static const struct intel_community tgllp_community1[] = { + TGL_COMMUNITY(0, 103, tgllp_community1_gpps), +}; + +static const struct intel_pinctrl_soc_data tgllp_community1_soc_data = { + .uid = "1", + .pins = tgllp_community1_pins, + .npins = ARRAY_SIZE(tgllp_community1_pins), + .communities = tgllp_community1, + .ncommunities = ARRAY_SIZE(tgllp_community1), +}; + +static const struct pinctrl_pin_desc tgllp_community4_pins[] = { + /* GPP_C */ + PINCTRL_PIN(0, "SMBCLK"), + PINCTRL_PIN(1, "SMBDATA"), + PINCTRL_PIN(2, "SMBALERTB"), + PINCTRL_PIN(3, "SML0CLK"), + PINCTRL_PIN(4, "SML0DATA"), + PINCTRL_PIN(5, "SML0ALERTB"), + PINCTRL_PIN(6, "SML1CLK"), + PINCTRL_PIN(7, "SML1DATA"), + PINCTRL_PIN(8, "UART0_RXD"), + PINCTRL_PIN(9, "UART0_TXD"), + PINCTRL_PIN(10, "UART0_RTSB"), + PINCTRL_PIN(11, "UART0_CTSB"), + PINCTRL_PIN(12, "UART1_RXD"), + PINCTRL_PIN(13, "UART1_TXD"), + PINCTRL_PIN(14, "UART1_RTSB"), + PINCTRL_PIN(15, "UART1_CTSB"), + PINCTRL_PIN(16, "I2C0_SDA"), + PINCTRL_PIN(17, "I2C0_SCL"), + PINCTRL_PIN(18, "I2C1_SDA"), + PINCTRL_PIN(19, "I2C1_SCL"), + PINCTRL_PIN(20, "UART2_RXD"), + PINCTRL_PIN(21, "UART2_TXD"), + PINCTRL_PIN(22, "UART2_RTSB"), + PINCTRL_PIN(23, "UART2_CTSB"), + /* GPP_F */ + PINCTRL_PIN(24, "CNV_BRI_DT"), + PINCTRL_PIN(25, "CNV_BRI_RSP"), + PINCTRL_PIN(26, "CNV_RGI_DT"), + PINCTRL_PIN(27, "CNV_RGI_RSP"), + PINCTRL_PIN(28, "CNV_RF_RESET_B"), + PINCTRL_PIN(29, "GPPC_F_5"), + PINCTRL_PIN(30, "CNV_PA_BLANKING"), + PINCTRL_PIN(31, "GPPC_F_7"), + PINCTRL_PIN(32, "I2S_MCLK2_INOUT"), + PINCTRL_PIN(33, "BOOTMPC"), + PINCTRL_PIN(34, "GPPC_F_10"), + PINCTRL_PIN(35, "GPPC_F_11"), + PINCTRL_PIN(36, "GSXDOUT"), + PINCTRL_PIN(37, "GSXSLOAD"), + PINCTRL_PIN(38, "GSXDIN"), + PINCTRL_PIN(39, "GSXSRESETB"), + PINCTRL_PIN(40, "GSXCLK"), + PINCTRL_PIN(41, "GMII_MDC"), + PINCTRL_PIN(42, "GMII_MDIO"), + PINCTRL_PIN(43, "SRCCLKREQB_6"), + PINCTRL_PIN(44, "EXT_PWR_GATEB"), + PINCTRL_PIN(45, "EXT_PWR_GATE2B"), + PINCTRL_PIN(46, "VNN_CTRL"), + PINCTRL_PIN(47, "V1P05_CTRL"), + PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"), + /* HVCMOS */ + PINCTRL_PIN(49, "L_BKLTEN"), + PINCTRL_PIN(50, "L_BKLTCTL"), + PINCTRL_PIN(51, "L_VDDEN"), + PINCTRL_PIN(52, "SYS_PWROK"), + PINCTRL_PIN(53, "SYS_RESETB"), + PINCTRL_PIN(54, "MLK_RSTB"), + /* GPP_E */ + PINCTRL_PIN(55, "SATAXPCIE_0"), + PINCTRL_PIN(56, "SPI1_IO_2"), + PINCTRL_PIN(57, "SPI1_IO_3"), + PINCTRL_PIN(58, "CPU_GP_0"), + PINCTRL_PIN(59, "SATA_DEVSLP_0"), + PINCTRL_PIN(60, "SATA_DEVSLP_1"), + PINCTRL_PIN(61, "GPPC_E_6"), + PINCTRL_PIN(62, "CPU_GP_1"), + PINCTRL_PIN(63, "SPI1_CS1B"), + PINCTRL_PIN(64, "USB2_OCB_0"), + PINCTRL_PIN(65, "SPI1_CSB"), + PINCTRL_PIN(66, "SPI1_CLK"), + PINCTRL_PIN(67, "SPI1_MISO_IO_1"), + PINCTRL_PIN(68, "SPI1_MOSI_IO_0"), + PINCTRL_PIN(69, "DDSP_HPD_A"), + PINCTRL_PIN(70, "ISH_GP_6"), + PINCTRL_PIN(71, "ISH_GP_7"), + PINCTRL_PIN(72, "GPPC_E_17"), + PINCTRL_PIN(73, "DDP1_CTRLCLK"), + PINCTRL_PIN(74, "DDP1_CTRLDATA"), + PINCTRL_PIN(75, "DDP2_CTRLCLK"), + PINCTRL_PIN(76, "DDP2_CTRLDATA"), + PINCTRL_PIN(77, "DDPA_CTRLCLK"), + PINCTRL_PIN(78, "DDPA_CTRLDATA"), + PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"), + /* JTAG */ + PINCTRL_PIN(80, "JTAG_TDO"), + PINCTRL_PIN(81, "JTAGX"), + PINCTRL_PIN(82, "PRDYB"), + PINCTRL_PIN(83, "PREQB"), + PINCTRL_PIN(84, "CPU_TRSTB"), + PINCTRL_PIN(85, "JTAG_TDI"), + PINCTRL_PIN(86, "JTAG_TMS"), + PINCTRL_PIN(87, "JTAG_TCK"), + PINCTRL_PIN(88, "DBG_PMODE"), +}; + +static const struct intel_padgroup tgllp_community4_gpps[] = { + TGL_GPP(0, 0, 23), /* GPP_C */ + TGL_GPP(1, 24, 48), /* GPP_F */ + TGL_GPP(2, 49, 54), /* HVCMOS */ + TGL_GPP(3, 55, 79), /* GPP_E */ + TGL_GPP(4, 80, 88), /* JTAG */ +}; + +static const struct intel_community tgllp_community4[] = { + TGL_COMMUNITY(0, 88, tgllp_community4_gpps), +}; + +static const struct intel_pinctrl_soc_data tgllp_community4_soc_data = { + .uid = "4", + .pins = tgllp_community4_pins, + .npins = ARRAY_SIZE(tgllp_community4_pins), + .communities = tgllp_community4, + .ncommunities = ARRAY_SIZE(tgllp_community4), +}; + +static const struct pinctrl_pin_desc tgllp_community5_pins[] = { + /* GPP_R */ + PINCTRL_PIN(0, "HDA_BCLK"), + PINCTRL_PIN(1, "HDA_SYNC"), + PINCTRL_PIN(2, "HDA_SDO"), + PINCTRL_PIN(3, "HDA_SDI_0"), + PINCTRL_PIN(4, "HDA_RSTB"), + PINCTRL_PIN(5, "HDA_SDI_1"), + PINCTRL_PIN(6, "GPP_R_6"), + PINCTRL_PIN(7, "GPP_R_7"), + /* SPI */ + PINCTRL_PIN(8, "SPI0_IO_2"), + PINCTRL_PIN(9, "SPI0_IO_3"), + PINCTRL_PIN(10, "SPI0_MOSI_IO_0"), + PINCTRL_PIN(11, "SPI0_MISO_IO_1"), + PINCTRL_PIN(12, "SPI0_TPM_CSB"), + PINCTRL_PIN(13, "SPI0_FLASH_0_CSB"), + PINCTRL_PIN(14, "SPI0_FLASH_1_CSB"), + PINCTRL_PIN(15, "SPI0_CLK"), + PINCTRL_PIN(16, "SPI0_CLK_LOOPBK"), +}; + +static const struct intel_padgroup tgllp_community5_gpps[] = { + TGL_GPP(0, 0, 7), /* GPP_R */ + TGL_GPP(1, 8, 16), /* SPI */ +}; + +static const struct intel_community tgllp_community5[] = { + TGL_COMMUNITY(0, 16, tgllp_community5_gpps), +}; + +static const struct intel_pinctrl_soc_data tgllp_community5_soc_data = { + .uid = "5", + .pins = tgllp_community5_pins, + .npins = ARRAY_SIZE(tgllp_community5_pins), + .communities = tgllp_community5, + .ncommunities = ARRAY_SIZE(tgllp_community5), +}; + +static const struct intel_pinctrl_soc_data *tgllp_soc_data_array[] = { + &tgllp_community0_soc_data, + &tgllp_community1_soc_data, + &tgllp_community4_soc_data, + &tgllp_community5_soc_data, + NULL +}; + +static const struct acpi_device_id tgl_pinctrl_acpi_match[] = { + { "INT34C5", (kernel_ulong_t)tgllp_soc_data_array }, + { } +}; +MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); + +static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops); + +static struct platform_driver tgl_pinctrl_driver = { + .probe = intel_pinctrl_probe_by_uid, + .driver = { + .name = "tigerlake-pinctrl", + .acpi_match_table = tgl_pinctrl_acpi_match, + .pm = &tgl_pinctrl_pm_ops, + }, +}; + +module_platform_driver(tgl_pinctrl_driver); + +MODULE_AUTHOR("Andy Shevchenko "); +MODULE_AUTHOR("Mika Westerberg "); +MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3-59-g8ed1b From 11b389cc05bf70b54e9154aa8ad034aa09111af5 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 6 Nov 2019 16:39:48 +0200 Subject: pinctrl: intel: Missed type change to unsigned int We converted 'unsigned' type to be 'unsigned int' in the driver, but there are couple of leftovers. So, finish the task now. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index b54b27228ad9..4860bc9a4e48 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1131,7 +1131,7 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, pending &= enabled; for_each_set_bit(gpp_offset, &pending, padgrp->size) { - unsigned irq; + unsigned int irq; irq = irq_find_mapping(gc->irq.domain, padgrp->gpio_base + gpp_offset); @@ -1181,7 +1181,7 @@ static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl, return ret; } -static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl) +static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) { const struct intel_community *community; unsigned int ngpio = 0; -- cgit v1.2.3-59-g8ed1b From 8ae93b5ed9bec003b77c1ffaca852388b8ca490e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 6 Nov 2019 16:39:48 +0200 Subject: pinctrl: cherryview: Missed type change to unsigned int We converted 'unsigned' type to be 'unsigned int' in the driver, but there are couple of leftovers. So, finish the task now. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index dff2a81250b6..582fa8a75559 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -165,7 +165,7 @@ struct chv_pinctrl { struct gpio_chip chip; struct irq_chip irqchip; void __iomem *regs; - unsigned intr_lines[16]; + unsigned int intr_lines[16]; const struct chv_community *community; u32 saved_intmask; struct chv_pin_context *saved_pin_context; @@ -1480,7 +1480,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) pending = readl(pctrl->regs + CHV_INTSTAT); for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) { - unsigned irq, offset; + unsigned int irq, offset; offset = pctrl->intr_lines[intr_line]; irq = irq_find_mapping(gc->irq.domain, offset); -- cgit v1.2.3-59-g8ed1b