From d16d0481e6bab5a916450e4ef0e1c958b550880c Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 9 Jun 2020 08:13:18 +0000 Subject: soc: amlogic: meson-gx-socinfo: Fix S905X3 and S905D3 ID's Correct the SoC revision and package bits/mask values for S905D3/X3 to detect a wider range of observed SoC IDs, and tweak sort order for A311D/S922X. S905X3 05 0000 0101 (SEI610 initial devices) S905X3 10 0001 0000 (ODROID-C4 and recent Android boxes) S905X3 50 0101 0000 (SEI610 later revisions) S905D3 04 0000 0100 (VIM3L devices in kernelci) S905D3 b0 1011 0000 (VIM3L initial production) Fixes commit c9cc9bec36d0 ("soc: amlogic: meson-gx-socinfo: Add SM1 and S905X3 IDs") Suggested-by: Neil Armstrong Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman Acked-by: Neil Armstrong Link: https://lore.kernel.org/r/20200609081318.28023-1-christianshewitt@gmail.com --- drivers/soc/amlogic/meson-gx-socinfo.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c index 01fc0d20a70d..6f54bd832c8b 100644 --- a/drivers/soc/amlogic/meson-gx-socinfo.c +++ b/drivers/soc/amlogic/meson-gx-socinfo.c @@ -66,10 +66,12 @@ static const struct meson_gx_package_id { { "A113D", 0x25, 0x22, 0xff }, { "S905D2", 0x28, 0x10, 0xf0 }, { "S905X2", 0x28, 0x40, 0xf0 }, - { "S922X", 0x29, 0x40, 0xf0 }, { "A311D", 0x29, 0x10, 0xf0 }, - { "S905X3", 0x2b, 0x5, 0xf }, - { "S905D3", 0x2b, 0xb0, 0xf0 }, + { "S922X", 0x29, 0x40, 0xf0 }, + { "S905D3", 0x2b, 0x4, 0xf5 }, + { "S905X3", 0x2b, 0x5, 0xf5 }, + { "S905X3", 0x2b, 0x10, 0x3f }, + { "S905D3", 0x2b, 0x30, 0x3f }, { "A113L", 0x2c, 0x0, 0xf8 }, }; -- cgit v1.2.3-59-g8ed1b From 95ca6f06dd4827ff63be5154120c7a8511cd9a41 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 17 Jun 2020 14:53:46 +0200 Subject: arm64: dts: meson: add missing gxl rng clock The peripheral clock of the RNG is missing for gxl while it is present for gxbb. Fixes: 1b3f6d148692 ("ARM64: dts: meson-gx: add clock CLKID_RNG0 to hwrng node") Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20200617125346.1163527-1-jbrunet@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index fc59c8534c0f..6c8b189884ca 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -337,6 +337,11 @@ }; }; +&hwrng { + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + &i2c_A { clocks = <&clkc CLKID_I2C>; }; -- cgit v1.2.3-59-g8ed1b From b2037dafcf082cd24b88ae9283af628235df36e1 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 18 Jun 2020 15:27:37 +0200 Subject: arm64: dts: meson-gxl-s805x: reduce initial Mali450 core frequency When starting at 744MHz, the Mali 450 core crashes on S805X based boards: lima d00c0000.gpu: IRQ ppmmu3 not found lima d00c0000.gpu: IRQ ppmmu4 not found lima d00c0000.gpu: IRQ ppmmu5 not found lima d00c0000.gpu: IRQ ppmmu6 not found lima d00c0000.gpu: IRQ ppmmu7 not found Internal error: synchronous external abort: 96000210 [#1] PREEMPT SMP Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.7.2+ #492 Hardware name: Libre Computer AML-S805X-AC (DT) pstate: 40000005 (nZcv daif -PAN -UAO) pc : lima_gp_init+0x28/0x188 ... Call trace: lima_gp_init+0x28/0x188 lima_device_init+0x334/0x534 lima_pdev_probe+0xa4/0xe4 ... Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b Reverting to a safer 666Mhz frequency on the S805X that doesn't use the GP0 PLL makes it more stable. Fixes: fd47716479f5 ("ARM64: dts: add S805X based P241 board") Fixes: 0449b8e371ac ("arm64: dts: meson: add libretech aml-s805x-ac board") Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200618132737.14243-1-narmstrong@baylibre.com --- .../dts/amlogic/meson-gxl-s805x-libretech-ac.dts | 2 +- .../boot/dts/amlogic/meson-gxl-s805x-p241.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi | 24 ++++++++++++++++++++++ 3 files changed, 26 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts index 6a226faab183..9e43f4dca90d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts @@ -10,7 +10,7 @@ #include #include -#include "meson-gxl-s905x.dtsi" +#include "meson-gxl-s805x.dtsi" / { compatible = "libretech,aml-s805x-ac", "amlogic,s805x", diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts index 867e30f1d62b..eb7f5a3fefd4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts @@ -9,7 +9,7 @@ #include -#include "meson-gxl-s905x.dtsi" +#include "meson-gxl-s805x.dtsi" / { compatible = "amlogic,p241", "amlogic,s805x", "amlogic,meson-gxl"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi new file mode 100644 index 000000000000..f9d705648426 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 BayLibre SAS + * Author: Neil Armstrong + */ + +#include "meson-gxl-s905x.dtsi" + +/ { + compatible = "amlogic,s805x", "amlogic,meson-gxl"; +}; + +/* The S805X Package doesn't seem to handle the 744MHz OPP correctly */ +&mali { + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; /* Glitch free mux */ + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, /* Do Nothing */ + <&clkc CLKID_MALI_0>; + assigned-clock-rates = <0>, /* Do Nothing */ + <666666666>, + <0>; /* Do Nothing */ +}; -- cgit v1.2.3-59-g8ed1b From 54320dcaa2522db3222c02d68b52cfed32a2e95b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 26 Jun 2020 10:06:26 +0200 Subject: ARM: dts: meson: Align L2 cache-controller nodename with dtschema Fix dtschema validator warnings like: l2-cache-controller@c4200000: $nodename:0: 'l2-cache-controller@c4200000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Kevin Hilman Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20200626080626.4080-1-krzk@kernel.org --- arch/arm/boot/dts/meson.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index ae89deaa8c9c..91129dc70d83 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -11,7 +11,7 @@ #size-cells = <1>; interrupt-parent = <&gic>; - L2: l2-cache-controller@c4200000 { + L2: cache-controller@c4200000 { compatible = "arm,pl310-cache"; reg = <0xc4200000 0x1000>; cache-unified; -- cgit v1.2.3-59-g8ed1b From d57c69ca6d4ab890e8edac5c8e10c7c2b54d500c Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 18 Jul 2020 05:45:05 +0000 Subject: arm64: dts: meson: update spifc node name on Khadas VIM3/VIM3L The VIM3/VIM3L Boards use w25q128 not w25q32 - this is a cosmetic change only - the device probes fine with the current device-tree. Fixes: 0e1610e726d3 ("arm64: dts: khadas-vim3: add SPIFC controller node") Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman Acked-by: Neil Armstrong Link: https://lore.kernel.org/r/20200718054505.4165-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 27408c10a811..6b75157265e1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -360,7 +360,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - w25q32: spi-flash@0 { + w25q128: spi-flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "winbond,w25q128fw", "jedec,spi-nor"; -- cgit v1.2.3-59-g8ed1b From 725da67ce4d77540d4d6f7ecc3ac5a885a684716 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 18 Jul 2020 07:25:31 +0000 Subject: arm64: dts: meson: add audio playback to odroid-c4 Add initial audio support limited to HDMI i2s. Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman Acked-by: Jerome Brunet Link: https://lore.kernel.org/r/20200718072532.8427-2-christianshewitt@gmail.com --- .../arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts | 88 ++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts index 00d90b30f8b4..cf5a98f0e47c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts @@ -8,6 +8,7 @@ #include "meson-sm1.dtsi" #include #include +#include / { compatible = "hardkernel,odroid-c4", "amlogic,sm1"; @@ -186,6 +187,69 @@ }; }; }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "SM1-ODROID-C4"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; }; &cpu0 { @@ -237,6 +301,18 @@ amlogic,tx-delay-ns = <2>; }; +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + &gpio { gpio-line-names = /* GPIOZ */ @@ -381,6 +457,18 @@ vqmmc-supply = <&flash_1v8>; }; +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + &uart_AO { status = "okay"; pinctrl-0 = <&uart_ao_a_pins>; -- cgit v1.2.3-59-g8ed1b From b8b85d01be916a30c9863a5456c218d802e01d97 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 18 Jul 2020 07:25:32 +0000 Subject: arm64: dts: meson: add audio playback to khadas-vim3l Add initial audio support limited to HDMI i2s, copying the config from the existing VIM3 device-tree. Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman Acked-by: Jerome Brunet Link: https://lore.kernel.org/r/20200718072532.8427-3-christianshewitt@gmail.com --- .../boot/dts/amlogic/meson-sm1-khadas-vim3l.dts | 88 ++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts index dbbf29a0dbf6..b104967dbef1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts @@ -8,6 +8,7 @@ #include "meson-sm1.dtsi" #include "meson-khadas-vim3.dtsi" +#include / { compatible = "khadas,vim3l", "amlogic,sm1"; @@ -31,6 +32,69 @@ regulator-boot-on; regulator-always-on; }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "SM1-KHADAS-VIM3L"; + audio-aux-devs = <&tdmout_a>; + audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", + "TDMOUT_A IN 1", "FRDDR_B OUT 0", + "TDMOUT_A IN 2", "FRDDR_C OUT 0", + "TDM_A Playback", "TDMOUT_A OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_a>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; }; &cpu0 { @@ -61,6 +125,18 @@ clock-latency = <50000>; }; +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; @@ -93,3 +169,15 @@ phy-names = "usb2-phy0", "usb2-phy1"; }; */ + +&tdmif_a { + status = "okay"; +}; + +&tdmout_a { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From 8b6f53d7b94b8d23860ae44a56b0af404a6c7e4c Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sun, 19 Jul 2020 02:14:20 +0000 Subject: dt-bindings: arm: amlogic: add support for the WeTek Core 2 The WeTek Core 2 is a commercial Android device based on the Amlogic Q200 reference design using the S912-H chipset. Specs: 3GB DDR3 RAM 32GB eMMC storage 10/100 Ethernet using Realtek RTL8152 (internal USB) 802.11 a/b/g/n/ac + BT 4.1 sdio wireless module (AP6356S) 2x single colour LEDs to indicate power 1x power button 1x reset button on the underside of the box HDMI 2.0 (4k@60p) video Composite video + 2-channel audio output on 3.5mm jack S/PDIF audio output 2x USB 2.0 ports 1x USB OTG port (internal) 1x micro SD card slot UART pins (internal) IR Sensor Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200719021421.7959-2-christianshewitt@gmail.com --- Documentation/devicetree/bindings/arm/amlogic.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 378229fa8310..5eba9f48823e 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -121,6 +121,7 @@ properties: - libretech,aml-s912-pc - nexbox,a1 - tronsmart,vega-s96 + - wetek,core2 - const: amlogic,s912 - const: amlogic,meson-gxm -- cgit v1.2.3-59-g8ed1b From ea232b9ccccf2f55fe231441f3908c31c7136c4f Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sun, 19 Jul 2020 02:14:21 +0000 Subject: arm64: dts: meson: add support for the WeTek Core 2 The WeTek Core2 is a commercial device based on the Amlogic Q200 reference design but with the following differences: - 3GB RAM, 32GB eMMC - Blue and Red LEDs used to signal on/off status - uart_AO can be accessed after opening the case; soldering required - USB OTG is not accessible (inside the case) - Realtek RTL8152 Ethernet (internal USB connection) Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20200719021421.7959-3-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/meson-gxm-wetek-core2.dts | 87 ++++++++++++++++++++++ 2 files changed, 88 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 5cac4d1d487d..4e2239ffcaa5 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts new file mode 100644 index 000000000000..ec794c134c15 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-gxm.dtsi" +#include "meson-gx-p23x-q20x.dtsi" +#include +#include + +/ { + compatible = "wetek,core2", "amlogic,s912", "amlogic,meson-gxm"; + model = "WeTek Core 2"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */ + }; + + leds { + compatible = "gpio-leds"; + + blue { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1710000>; + + button-update { + label = "update"; + linux,code = ; + press-threshold-microvolt = <10000>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + button-power { + label = "power"; + linux,code = ; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* Disabled as Realtek RTL8152 USB provides Ethernet */ +ðmac { + status = "disabled"; +}; + +&internal_phy { + status = "disabled"; +}; + +&ir { + linux,rc-map-name = "rc-wetek-play2"; +}; + +/* This is connected to the Bluetooth module: */ +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + }; +}; -- cgit v1.2.3-59-g8ed1b From 46ffadc7e658277d7559899d7f641f14a3cfae8c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 19 Jul 2020 19:32:11 +0200 Subject: arm64: dts: amlogic: meson-gx: add the Mali-450 OPP table and use DVFS Add the OPP table for the Mali-450 GPU and drop the hardcoded initial clock configuration. This enables GPU DVFS and thus saves power when the GPU is not in use while still being able switch to a higher clock on demand. Set the GP0_PLL clock to 744MHz (which is the only frequency which cannot be derived from the FCLK dividers) as the clock driver avoids setting the parent clock rates so the MPLL clocks aren't changed (as these are reserved for audio). The only exception to this is the GXL S805X package because the 744MHz OPP isn't working correctly there. While here, make most of meson-gxl-mali re-usable to reduce the amount of duplicate code between GXBB and GXL. This is more important now as we don't want to duplicate the GPU OPP table. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200719173213.639540-2-martin.blumenstingl@googlemail.com --- arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi | 61 +++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 51 ++++--------------- arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi | 46 ++++------------- arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi | 17 +++---- 4 files changed, 89 insertions(+), 86 deletions(-) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi new file mode 100644 index 000000000000..f9771b51c852 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 BayLibre SAS + * Author: Neil Armstrong + */ + +/ { + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <950000>; + }; + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <950000>; + }; + opp-285714285 { + opp-hz = /bits/ 64 <285714285>; + opp-microvolt = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <950000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + }; + opp-666666666 { + opp-hz = /bits/ 64 <666666666>; + opp-microvolt = <950000>; + }; + opp-744000000 { + opp-hz = /bits/ 64 <744000000>; + opp-microvolt = <950000>; + }; + }; +}; + +&apb { + mali: gpu@c0000 { + compatible = "arm,mali-450"; + reg = <0x0 0xc0000 0x0 0x40000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2"; + operating-points-v2 = <&gpu_opp_table>; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index ea50dd434887..7c029f552a23 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -4,6 +4,7 @@ */ #include "meson-gx.dtsi" +#include "meson-gx-mali450.dtsi" #include #include #include @@ -264,46 +265,6 @@ }; }; -&apb { - mali: gpu@c0000 { - compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_GP0_PLL>, - <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <0>, /* Do Nothing */ - <&clkc CLKID_GP0_PLL>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <744000000>, - <0>, /* Do Nothing */ - <744000000>, - <0>; /* Do Nothing */ - }; -}; - &cbus { spifc: spi@8c80 { compatible = "amlogic,meson-gxbb-spifc"; @@ -386,6 +347,16 @@ clocks = <&clkc CLKID_I2C>; }; +&mali { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + + assigned-clocks = <&clkc CLKID_GP0_PLL>; + assigned-clock-rates = <744000000>; +}; + &periphs { pinctrl_periphs: pinctrl@4b0 { compatible = "amlogic,meson-gxbb-periphs-pinctrl"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi index 6aaafff674f9..478e755cc87c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi @@ -4,42 +4,14 @@ * Author: Neil Armstrong */ -&apb { - mali: gpu@c0000 { - compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; +#include "meson-gx-mali450.dtsi" - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_GP0_PLL>, - <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <0>, /* Do Nothing */ - <&clkc CLKID_GP0_PLL>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <744000000>, - <0>, /* Do Nothing */ - <744000000>, - <0>; /* Do Nothing */ - }; +&mali { + compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; + + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + + assigned-clocks = <&clkc CLKID_GP0_PLL>; + assigned-clock-rates = <744000000>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi index f9d705648426..29975849822c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi @@ -11,14 +11,13 @@ }; /* The S805X Package doesn't seem to handle the 744MHz OPP correctly */ +&gpu_opp_table { + opp-744000000 { + status = "disabled"; + }; +}; + &mali { - assigned-clocks = <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>; /* Do Nothing */ + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; }; -- cgit v1.2.3-59-g8ed1b From 8f16cfabbc0a6c52b114eca2ff8e95bb07949741 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 19 Jul 2020 19:32:12 +0200 Subject: arm64: dts: amlogic: meson-gxm: add the Mali OPP table and use DVFS Add the OPP table for the Mali-T820 GPU and drop the hardcoded initial clock configuration. This enables GPU DVFS and thus saves power when the GPU is not in use while still being able switch to a higher clock on demand. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200719173213.639540-3-martin.blumenstingl@googlemail.com --- arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 45 ++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi index 40e3e123e05b..fe4145112295 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi @@ -82,6 +82,35 @@ #cooling-cells = <2>; }; }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <950000>; + }; + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <950000>; + }; + opp-285714285 { + opp-hz = /bits/ 64 <285714285>; + opp-microvolt = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <950000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + }; + opp-666666666 { + opp-hz = /bits/ 64 <666666666>; + opp-microvolt = <950000>; + }; + }; }; &apb { @@ -106,21 +135,7 @@ interrupt-names = "job", "mmu", "gpu"; clocks = <&clkc CLKID_MALI>; resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>; /* Do Nothing */ + operating-points-v2 = <&gpu_opp_table>; }; }; -- cgit v1.2.3-59-g8ed1b From 916a0edc43f03f86b13fbc9943e5dc936671ea6e Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 19 Jul 2020 19:32:13 +0200 Subject: arm64: dts: amlogic: meson-g12: add the Mali OPP table and use DVFS Add the OPP table for the Mali Bifrost GPU and drop the hardcoded initial clock configuration. This enables GPU DVFS and thus saves power when the GPU is not in use while still being able switch to a higher clock on demand. Set the GP0_PLL clock to 744MHz (which is the only frequency which cannot be derived from the FCLK dividers) as the clock driver avoids setting the parent clock rates so the HIFI PLL clock isn't changed (as that's reserved for audio). Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200719173213.639540-4-martin.blumenstingl@googlemail.com --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 49 ++++++++++++++++------- 1 file changed, 34 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 41805f2ed8fc..1e83ec5b8c91 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -52,6 +52,39 @@ secure-monitor = <&sm>; }; + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-124999998 { + opp-hz = /bits/ 64 <124999998>; + opp-microvolt = <800000>; + }; + opp-249999996 { + opp-hz = /bits/ 64 <249999996>; + opp-microvolt = <800000>; + }; + opp-285714281 { + opp-hz = /bits/ 64 <285714281>; + opp-microvolt = <800000>; + }; + opp-399999994 { + opp-hz = /bits/ 64 <399999994>; + opp-microvolt = <800000>; + }; + opp-499999992 { + opp-hz = /bits/ 64 <499999992>; + opp-microvolt = <800000>; + }; + opp-666666656 { + opp-hz = /bits/ 64 <666666656>; + opp-microvolt = <800000>; + }; + opp-799999987 { + opp-hz = /bits/ 64 <799999987>; + opp-microvolt = <800000>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -2362,21 +2395,7 @@ interrupt-names = "job", "mmu", "gpu"; clocks = <&clkc CLKID_MALI>; resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <800000000>, - <0>; /* Do Nothing */ + operating-points-v2 = <&gpu_opp_table>; #cooling-cells = <2>; }; }; -- cgit v1.2.3-59-g8ed1b